US5341336A
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Method for stress testing decoders and periphery circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1993-04-30
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Granted: 1994-08-23
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Expires: 2013-04-30
Abstract
Abstract A method for stress testing decoders and other periphery circuits used with a memory array. An address buffer simultaneously sets the inputs of a plurality of decoders to a first common voltage level, so that a plurality of rows and/or columns within the memory array are selected for a predetermined period of time. A stress voltage is then applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits. The inputs of the plurality of decoders are then simultaneously set to a second common voltage level, so that the plurality of rows and/or columns within the memory array are deselected. Finally, a stress voltage is applied to the integrated circuit to stress test the gate oxides within the decoders and other periphery circuits.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:24
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
101 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 2
Independent Claim
101 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 3
Dependent Claim
44 words
The method of claim 1, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level.
Claim 4
Dependent Claim
69 words
The method of claim 1, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the first common voltage level further comprises the step of simultaneously setting the inputs of a plurality of column decoding circuits to the first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time.
Claim 5
Dependent Claim
63 words
The method of claim 3, wherein the step of simultaneously setting the inputs of the plurality of row decoding circuits to the second common voltage level further comprises the step of simultaneously setting the inputs of a plurality of column decoding circuits to the second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected.
Claim 6
Dependent Claim
43 words
The method of claim 1, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the first common voltage level comprises simultaneously setting the inputs of the plurality of row decoding circuits to a high voltage level.
Claim 7
Dependent Claim
43 words
The method of claim 5, wherein said step of simultaneously setting the inputs of the plurality of row decoding circuits to the second common voltage level comprises simultaneously setting the inputs of the plurality of row decoding circuits to a low voltage level.
Claim 8
Independent Claim
121 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time, wherein a bit line load of a bit line pair is turned off during selection of a plurality of rows; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 9
Independent Claim
121 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time, wherein a bit line load of a bit line pair is turned off during selection of a plurality of rows; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 10
Dependent Claim
18 words
The method of claim 7, wherein the bit line load is pulled to ground after being turned off.
Claim 11
Independent Claim
132 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.
Claim 12
Independent Claim
132 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a second common voltage level, wherein the plurality of rows within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.
Claim 13
Independent Claim
109 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 14
Independent Claim
109 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 15
Dependent Claim
44 words
The method of claim 10, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level.
Claim 16
Dependent Claim
65 words
The method of claim 10, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the first common voltage level further comprises the step of simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time.
Claim 17
Independent Claim
164 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein a bit line load of a bit line pair is turned off during selection of the plurality of rows.
Claim 18
Independent Claim
164 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein a bit line load of a bit line pair is turned off during selection of the plurality of rows.
Claim 19
Dependent Claim
18 words
The method of claim 13, wherein the bit line load is pulled to ground after being turned off.
Claim 20
Dependent Claim
59 words
The method of claim 12, wherein the step of simultaneously setting the inputs of the plurality of column decoding circuits to the second common voltage level further comprises the step of simultaneously setting the inputs of a plurality of row decoding circuits to the second common voltage level, wherein the plurality of rows within the memory array are deselected.
Claim 21
Dependent Claim
43 words
The method of claim 10, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the first common voltage level comprises simultaneously setting the inputs of the plurality of column decoding circuits to a high voltage level.
Claim 22
Dependent Claim
43 words
The method of claim 16, wherein said step of simultaneously setting the inputs of the plurality of column decoding circuits to the second common voltage level comprises simultaneously setting the inputs of the plurality of column decoding circuits to a low voltage level.
Claim 23
Independent Claim
175 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.
Claim 24
Independent Claim
175 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of column decoding circuits to a first common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for a predetermined period of time and simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of column decoding circuits to a second common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit; wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.
Claim 25
Independent Claim
171 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; simultaneously setting the inputs of a plurality of column decoding circuits to a second common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for the predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a third common voltage level, wherein the plurality of rows within the memory array are deselected; simultaneously setting the inputs of the plurality of column decoding circuits to a fourth common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 26
Independent Claim
171 words
A method for stress testing decoders and periphery circuits used with a memory array in an integrated circuit, comprising the steps of: simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level, wherein a plurality of rows within the memory array are selected for a predetermined period of time; simultaneously setting the inputs of a plurality of column decoding circuits to a second common voltage level, wherein a plurality of bit and complementary bit lines within the memory array are selected for the predetermined period of time; applying a stress voltage to the integrated circuit; simultaneously setting the inputs of the plurality of row decoding circuits to a third common voltage level, wherein the plurality of rows within the memory array are deselected; simultaneously setting the inputs of the plurality of column decoding circuits to a fourth common voltage level, wherein the plurality of bit and complementary bit lines within the memory array are deselected; and applying a stress voltage to the integrated circuit.
Claim 27
Dependent Claim
44 words
The method of claim 19, further comprising the step of placing the integrated circuit in a test or special operating mode prior to performing the step of simultaneously setting the inputs of a plurality of row decoding circuits to a first common voltage level.
Claim 28
Dependent Claim
43 words
The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of row decoding circuits to the first common voltage level comprises simultaneously setting the inputs of a plurality of row decoding circuits to a low voltage level.
Claim 29
Dependent Claim
43 words
The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of column decoding circuits to the second common voltage level comprises simultaneously setting the inputs of a plurality of column decoding circuits to a low voltage level.
Claim 30
Dependent Claim
43 words
The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of row decoding circuits to the third common voltage level comprises simultaneously setting the inputs of a plurality of row decoding circuits to a high voltage level.
Claim 31
Dependent Claim
43 words
The method of claim 19, wherein said step of simultaneously setting the inputs of a plurality of column decoding circuits to the fourth common voltage level comprises simultaneously setting the inputs of a plurality of column decoding circuits to a high voltage level.
Claim 32
Dependent Claim
25 words
The method of claim 19, wherein a bit line load of a bit line pair is turned off during selection of a plurality of rows.
Claim 33
Dependent Claim
18 words
The method of claim 25, wherein the bit line load is pulled to ground after being turned off.
Claim 34
Dependent Claim
36 words
The method of claim 19, wherein said steps of setting the inputs of a plurality of row decoding circuits or column decoding circuits are performed when the stress voltage is set to a low voltage level.
References Cited (Backward Citations)
US4651304A
Cited
US5208776A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |