US5208776A
Expired / Lapsed
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Pulse generation circuit
Assignee: Texas Instruments Inc
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Filing: 1990-07-31
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Granted: 1993-05-04
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Expires: 2010-07-31
Abstract
Abstract A pulse generation circuit is disclosed. The pulse generation circuit has a serially connected chain of delay elements, the first delay element for receiving an input pulse. It has a plurality of logic gates with each logic gate having one input coupled to the output of one delay element in the chain. The other input is coupled to the output of the next delay element in the chain. When the input pulse is received, the outputs of the logic gates form a plurality of non-overlapping pulses. Such a circuit is useful in a semiconductor memory device as a phase delay circuit.
Inventors
- 👤 Takumi Nasu
- 👤 Hugh P. McAdams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 23:03
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G06; G06F; G06F11/00; G06F11/22; G06F11/2273; G11C29/04; G11C29/50
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
78 words
A pulse generation circuit comprising: a serially connected chain of delay elements, the first delay element for receiving an input pulse; and a plurality of logic gates, each logic gate having one input coupled to an output of a delay element in the chain another input coupled to the output of the next delay element in the chain such that when the input pulse is received, the outputs of the logic gates form a plurality of non-overlapping pulses.
Claim 2
Dependent Claim
78 words
A pulse generation circuit comprising: a serially connected chain of delay elements, the first delay element for receiving an input pulse; and a plurality of logic gates, each logic gate having one input coupled to an output of a delay element in the chain another input coupled to the output of the next delay element in the chain such that when the input pulse is received, the outputs of the logic gates form a plurality of non-overlapping pulses.
Claim 3
Dependent Claim
13 words
The pulse generation circuit of claim 1 wherein the delay elements are inverters.
Claim 4
Dependent Claim
15 words
The pulse generation circuit of claim 2 wherein the logic gates are NAND logic gates.
Claim 5
Dependent Claim
18 words
The pulse generation circuit of claim 1 further comprising: capacitors connected to the outputs of the delay elements.
Claim 6
Dependent Claim
62 words
A dynamic memory device integrated onto a single semiconductor substrate comprising: an array of memory cells; support circuitry to read information from the memory cells and write information to the memory cells; redundant memory cells to replace defective memory cells; redundant circuits to access the redundant memory cells; circuitry to activate various of the redundant circuits at different times during power up.
Claim 7
Dependent Claim
62 words
A dynamic memory device integrated onto a single semiconductor substrate comprising: an array of memory cells; support circuitry to read information from the memory cells and write information to the memory cells; redundant memory cells to replace defective memory cells; redundant circuits to access the redundant memory cells; circuitry to activate various of the redundant circuits at different times during power up.
Claim 8
Dependent Claim
81 words
The dynamic memory device of claim 5 wherein the circuitry to activate comprises: a serially connected chain of delay elements, the first delay element for receiving a power up reset pulse; a plurality of logic gates, each logic gate having one input coupled to an output of a delay element in the chain, another input coupled to a output of the following delay element in the chain, the outputs of the logic gates forming a series of phase delayed reset pulses.
Claim 9
Dependent Claim
14 words
The dynamic memory device of claim 6 wherein the delay elements are CMOS inverters.
Claim 10
Dependent Claim
15 words
The dynamic memory device of claim 7 wherein the logic gates are NAND logic gates.
References Cited (Backward Citations)
US4802127A
Cited
US4985865A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-03 | 1996-11-02 | 1997-05-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-03 | 2000-11-02 | 2001-05-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-03 | 2004-11-02 | 2005-05-04 | $7700.00 | Window Closed / Lapsed |