US4802127A
Expired / Lapsed
US
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Output buffer circuit for a semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1988-05-18
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Granted: 1989-01-31
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Expires: 2008-05-18
Abstract
Abstract A semiconductor memory device of multi-bit type which produces plural output signals corresponding to read-out data from one address at a time including memory device for storing data. In a plurality of output buffer stages for producing the output signals, the operation of the output buffer stages is based upon at least a timing signal. A device for operating the output buffer stages have predetermined time differences. The output signals having predetermined time differences are delivered from the output buffer stages.
Inventors
- 👤 Takao Akaogi
- 👤 Takeo Tatematsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 05:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; G11C7/22
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
146 words
A multi-bit semiconductor memory device having a plurality of output buffer circuits, each of said output buffer circuits comprising: a data output terminal; an output switching means for pulling up a potential of said data output terminal to a HIGH level; a charge discharging switching means for pulling down the potential of said data output terminal to a LOW level; driving means for driving said output switching means to respond to read-out data; and delay means connected between a drive terminal connected with said output switching means and said charge discharging switching means; wherein said charge discharging switching means carries out a pull-down operation in response to an output of said delay means, each said delay means of said output buffer circuits provides different delay times from each other, so that the timings of pull-down operations in said output buffer circuits are shifted with each other.
Claim 2
Dependent Claim
146 words
A multi-bit semiconductor memory device having a plurality of output buffer circuits, each of said output buffer circuits comprising: a data output terminal; an output switching means for pulling up a potential of said data output terminal to a HIGH level; a charge discharging switching means for pulling down the potential of said data output terminal to a LOW level; driving means for driving said output switching means to respond to read-out data; and delay means connected between a drive terminal connected with said output switching means and said charge discharging switching means; wherein said charge discharging switching means carries out a pull-down operation in response to an output of said delay means, each said delay means of said output buffer circuits provides different delay times from each other, so that the timings of pull-down operations in said output buffer circuits are shifted with each other.
Claim 3
Dependent Claim
16 words
A device according to claim 1, wherein said output buffer circuits comprise complementary MOS transistor inverters.
Claim 4
Dependent Claim
15 words
A device according to claim 1, wherein said output buffer circuits comprise push-pull buffer circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |