Anti-noise and auto-stand-by memory architecture

Claim 5

A memory device comprising, functionally organized in cascade, at least an input circuitry, a control circuitry, a decoding and selection circuitry, a matrix of memory cells organized in rows and columns, a sense amplifier circuit, a circuit for storing extracted data and an output buffer which is controlled through an enabling line connected to said control circuitry, each of said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit having a respective propagation delay for a signal therethrough, further comprising: a transition detecting circuit, functionally connected to said input circuitry and capable of generating on an output a pulse for any signal transition detected in said input circuitry; a dummy circuit chain, capable of replicating said respective propagation delays of a signal through said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit and consisting of substantially homologous circuits connected in cascade and individually enableable by means of a reset signal, having an input connected to the output of said detecting circuit and an output; a one shot pulse generating circuit having an input connected to the output of said dummy chain and an output connected to an enabling input of said extracted data storing circuit; a reset signal generating circuit having a first input connected to the output of said one-shot pulse generating circuit, a second input connected to the output of said transition detecting circuit and an output connected to a reset terminal of said homologous circuits of said dummy circuit chain and a reset terminal of said one-shot pulse generating circuit; the device preventing any modification of a data output value of said extracted data storage circuit for any transition of signals occurring after an interval of time following a first transition in said input circuitry, as detected by said detecting circuit, which is shorter than the propagation time of a pulse through said dummy circuit chain.

Claim 6

A memory device comprising, functionally organized in cascade, at least an input circuitry, a control circuitry, a decoding and selection circuitry, a matrix of memory cells organized in rows and columns, a sense amplifier circuit, a circuit for storing extracted data and an output buffer which is controlled through an enabling line connected to said control circuitry, each of said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit having a respective propagation delay for a signal therethrough, further comprising: a transition detecting circuit, functionally connected to said input circuitry and capable of generating on an output a pulse for any signal transition detected in said input circuitry; a dummy circuit chain, capable of replicating said respective propagation delays of a signal through said decoding and selection circuitry, said memory matrix, and said sense amplifier circuit and consisting of substantially homologous circuits connected in cascade and individually enableable by means of a reset signal, having an input connected to the output of said detecting circuit and an output; a one shot pulse generating circuit having an input connected to the output of said dummy chain and an output connected to an enabling input of said extracted data storing circuit; a reset signal generating circuit having a first input connected to the output of said one-shot pulse generating circuit, a second input connected to the output of said transition detecting circuit and an output connected to a reset terminal of said homologous circuits of said dummy circuit chain and a reset terminal of said one-shot pulse generating circuit; the device preventing any modification of a data output value of said extracted data storage circuit for any transition of signals occurring after an interval of time following a first transition in said input circuitry, as detected by said detecting circuit, which is shorter than the propagation time of a pulse through said dummy circuit chain.

Claim 7

A memory device as defined in claim 3 wherein said decoding and selection circuitry and said sense amplifier circuit are respectively provided with an enable signal input terminal and a disable signal input terminal connected to the output of said transition detecting circuit and to the output of said reset signal generating circuit, respectively.

Claim 8

A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry and memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough further comprising: a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit chain, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit chain including a plurality of circuits connected in cascade including a dummy selection circuitry, a dummy memory cell circuitry, and a dummy sense amplifier circuitry, each dummy circuitry individually having a delay that is similar to the delay of the corresponding memory circuitry; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit chain and an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit from the dummy circuit chain.

Claim 9

A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry and memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough further comprising: a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit chain, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit chain including a plurality of circuits connected in cascade including a dummy selection circuitry, a dummy memory cell circuitry, and a dummy sense amplifier circuitry, each dummy circuitry individually having a delay that is similar to the delay of the corresponding memory circuitry; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit chain and an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit from the dummy circuit chain.

Claim 10

The memory device according to claim 5, further including a reset signal generating circuit having a first input connected to the output of said enable signal generating circuit, a second input connected to the output of the transition detecting circuit, and an output connected to a respective reset terminal of the dummy selection circuitry, the dummy memory cell circuitry, and the dummy sense amplifier circuitry.

Claim 11

The memory device according to claim 6, further including an electrical connection between the output of said reset signal generating circuit and said enable signal generating circuit for resetting said enable signal generating circuit.

Claim 12

The memory device according to claim 5, further including electronic circuitry connecting the output of said dummy sense amplifier to an input of said memory sense amplifier circuitry to enable said memory sense amplifier circuitry.

Claim 13

The memory device according to claim 5 wherein said dummy selection circuitry includes circuitry which is similar in electrical connection and structure to the memory selection circuitry to accurately simulate the approximate time for the propagation of the signal through said memory selection circuitry, said dummy selection circuitry and said memory selection circuitry having approximately the same propagation delay time.

Claim 14

The memory device according to claim 5 wherein said enable signal generating circuit is a one-shot circuit.

Claim 15

The memory device according to claim 5 wherein said dummy memory circuitry further includes: a dummy bit line for receiving a bit line selection signal; a dummy word line for receiving a dummy word line signal; and a dummy memory cell for outputting dummy data upon being selected by said dummy bit line and said dummy word line.

Claim 16

The memory device according to claim 5, further including: an enable signal input terminal connected to said memory selection circuitry; an enable signal input terminal connected to said memory sense amplifier circuitry; and electrical circuitry connecting the output of said transition detecting circuit to the enable input terminals of said memory selection circuitry and said memory sense amplifier circuitry respectively.

Claim 17

The memory device according to claim 5 when said dummy circuit chain has fewer elements in cascade than are in the memory chain, said dummy circuit chain including delay circuits that simulate the propagation time of the signal through the memory chain.

Claim 18

A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry, memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough, further comprising: a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit having a delay that is similar to the delay of the corresponding memory circuit chain; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit upon receiving a signal from the dummy circuit.

Claim 19

A memory device having a memory chain including an input address circuitry, memory selection circuitry, memory cell circuitry, memory sense amplifier circuitry, and memory output circuitry, each of the memory circuitries being organized in cascade and having a propagation delay time for a signal propagating therethrough, further comprising: a transition detecting circuitry, functionally connected to said input address circuitry and capable of generating an output pulse for an address signal transition detected in said input address circuitry; a dummy circuit, capable of replicating a similar propagation delay as a signal through said memory selection circuitry, said memory cell circuitry, and said sense amplifier circuitry, the dummy circuit having a delay that is similar to the delay of the corresponding memory circuit chain; and an enable signal generating circuit having an input functionally connected to the output of said dummy circuit an output connected to an enabling input of said memory output circuitry for enabling the memory output circuitry to output sensed memory data from said memory sense amplifier circuitry only when enabled via the enable signal generating circuit upon receiving a signal from the dummy circuit.

Claim 20

The memory device of claim 14 wherein said dummy circuit has fewer elements than said memory chain to achieve the similar propagative delay to the propagation delay through the memory chain with circuits that are not replicates of the circuits in the memory chain.

Claim 21

The memory device of claim 14 wherein said dummy circuit includes a chain of dummy circuits that are replicates of circuits in the memory circuit chain to achieve the similar propagation delay to the propagation delay through the memory circuit chain.

Claim 22

The memory device of claim 14 wherein said dummy circuit further includes a reset circuit having an input connected to the transition detecting circuitry and having an output connected to the input of the dummy circuit to prevent the dummy circuit from propagating a signal until the reset circuit output changes state and to prevent the further propagation of any signal from propagating in the dummy circuit when the reset circuit output changes state.