EP0090590A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Fujitsu Ltd
•
Filing: 1983-03-23
•
Granted: —
•
Expires: 2003-03-23
Abstract
Abstract A semiconductor memory device such as a static-type random-access memory device comprising an address-change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a selected memory cell. The readout signal is input into the latch circuit in synchronization with the timing of the pulse signal or a short time after the pulse signal, and the readout data from the semiconductor memory device is obtained from the latch circuit, thereby increasing the time interval during which the readout data from the semiconductor memory device is available.
Inventors
- 👤 Keizo Aoyama
- 👤 Takahiko Yamauchi
- 👤 Teruo Dai-2-Yayoi-So 5 Seki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 17:26
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/106; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
78 words
A semiconductor memory device characterized in that said semiconductor memory device comprises an address--change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a memory cell, said readout signal being input into said latch circuit in response to the supply of said pulse signal or the delayed signal of said pulse signal and the readout data being obtained from said latch circuit.
Claim 2
Dependent Claim
78 words
A semiconductor memory device characterized in that said semiconductor memory device comprises an address--change detection circuit which generates a pulse signal when an input address signal has changed and a latch circuit which temporarily stores the readout signal from a memory cell, said readout signal being input into said latch circuit in response to the supply of said pulse signal or the delayed signal of said pulse signal and the readout data being obtained from said latch circuit.
Claim 3
Dependent Claim
51 words
A semiconductor memory device according to claim 1, wherein said latch circuit receives the output signal of a sense amplifier which amplifies a readout signal from a memory cell, the output signal of said latch circuit being output as a readout signal of said semiconductor memory device via an output buffer.
Claim 4
Dependent Claim
43 words
A semiconductor memory device according to claim 2, wherein said output signal of said sense amplifier is stored in said latch circuit in response to the output pulse of a delay circuit which delays said pulse signal generated by said address-change detection circuit.
Claim 5
Dependent Claim
36 words
A semiconductor memory device according to claim 2 or 3, wherein said latch circuit comprises two NOR gates and a flip-flop circuit which is set or reset by the output signals of said two NOR gates.
Claim 6
Dependent Claim
39 words
A semiconductor memory device according to claim 4, wherein each of said NOR gates receives said pulse signal from said address-change detection circuit or said delayed signal of said pulse signal and an output signal of said sense amplifier.
Claim 7
Dependent Claim
25 words
A semiconductor memory device according to claim 4, wherein each of said NOR gates comprises two inverter transistors parallelly connected and a common load transistor.
Claim 8
Dependent Claim
80 words
A semiconductor memory device according to claim 4, wherein said flip-flop circuit comprises a pair of cross--coupled transistors, a pair of input transistors, each of which is parallelly connected to one of said pair of cross-coupled transistors and each of which receives at the gate electrode thereof the output signal of one of said NOR gates, and a pair of load transistors, each of which is connected between the drain of one of said cross-coupled transistors and a power source.
Claim 9
Dependent Claim
29 words
A semiconductor memory device according to claim 1, wherein said address-change detection circuit generates said pulse signal when at least one bit of said input address signal has changed.
Claim 10
Dependent Claim
23 words
A semiconductor memory device according to claim 8, wherein said input address signal includes a column address signal and a row address signal.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.