Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC-MN), at least one word line (Wl to WD) coupled to said semiconductor memory cells for selectively transmitting an access signal thereto, at least one pair of data lines (DO-1 to DO-M and Dl-1 to Dl-M) coupled to said plurality of semiconductor memory cells for transferring data with respect thereto, a sense amplifier means (SA-1 to SA-M) coupled to said at least one pair of data lines for amplifying a data signal transferred therethrough, and energizing signal generating means (22) for producing an energizing signal for activating said sense amplifier means, characterized by: a dummy word line (WD) having a signal transfer property coresponding to that of said at least one word line (Wl to WN), and a dummy selection signal generating means (20) coupled to said dummy word line for supplying a dummy selection signal to said energizing signal generating means (22) through said dummy word line for causing said energizing signal generating means to supply an energizing signal to said sense amplifier means (SA-1 to SA-M) every time an addressing operation is effected.

Claim 3

A semiconductor memory device according to claim 1, which further comprises capacitive means (Cl to CM) coupled to said dummy word line.

Claim 4

A semiconductor memory device according to claim 2, wherein said capacitive means (Cl to CM) includes at least one MOS capacitor.

Claim 5

A semiconductor memory device according to claim 1 or 2, which further comprises a column decoder (4) for selectively energizing said at least one pair of data lines, and a pair of input/output lines (9-1, 9-2) coupled to said at least one pair of data lines through said column decoder.

Claim 6

A semiconductor memory device according to claim 4, wherein said sense amplifier means includes a sense amplifier (400) having input/output terminals coupled to said input/output lines for amplifying a data signal on said input/output lines in response to an output signal from said energizing signal generating means.

Claim 7

A semiconductor memory device according to claim 1 or 4, which further comprises precharge means (6) coupled to said at least one pair of data lines for setting said data lines to an equal potential level every time an address designating operation is effected.

Claim 8

A semiconductor memory device according to claim 1 or 2, wherein said sense amplifier means includes at least one sense amplifier (SA-1 to SA-M) coupled to said at least one pair of data lines for amplifying a data signal on said at least one pair of data lines in response to an output signal from said energizing signal generating means.

Claim 9

A semiconductor memory device according to claim 1 or 2, wherein said dummy word line is made practically of the same semiconductor material as that of said at least one word line.

Claim 10

A semiconductor memory device according to claim 1 or 2, which further comprises decoding means (200, 202) for selectively energizing said at least one word line, said decoding means and said dummy selection signal generating means having practically the same response time characteristic.

Claim 11

A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC- MN ) arranged in a matrix array, a plurality of word lines (Wl to WN) each commonly coupled to the semiconductor memory cells in each row of said matrix array, a plurality of pairs of data lines (DO-1 to DO-M and DI-I to Dl-M) each pair commonly coupled to the semiconductor memory cells in each column of said matrix array for the transfer of data with respect to these memory cells, sense amplifier means (SA-1 to SA-M) coupled to said plurality of pairs of data lines for amplifying data transferred through one of said data line pairs, and energizing means (22) for producing an energizing signal for activating said sense amplifier means, characterized by: a dummy word line (WD) having a signal transfer property corresponding to those of said word lines, and dummy selection signal generating means (20) coupled to said dummy word line for supplying a dummy selection signal to said energizing signal generating means (22) through said dummy word line for causing said energizing signal generating means to supply an energizing signal to said sense amplifier means (SA-1 to SA-M) every time an addressing operation is effected.

Claim 12

A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC- MN ) arranged in a matrix array, a plurality of word lines (Wl to WN) each commonly coupled to the semiconductor memory cells in each row of said matrix array, a plurality of pairs of data lines (DO-1 to DO-M and DI-I to Dl-M) each pair commonly coupled to the semiconductor memory cells in each column of said matrix array for the transfer of data with respect to these memory cells, sense amplifier means (SA-1 to SA-M) coupled to said plurality of pairs of data lines for amplifying data transferred through one of said data line pairs, and energizing means (22) for producing an energizing signal for activating said sense amplifier means, characterized by: a dummy word line (WD) having a signal transfer property corresponding to those of said word lines, and dummy selection signal generating means (20) coupled to said dummy word line for supplying a dummy selection signal to said energizing signal generating means (22) through said dummy word line for causing said energizing signal generating means to supply an energizing signal to said sense amplifier means (SA-1 to SA-M) every time an addressing operation is effected.

Claim 13

A semiconductor memory device according to claim 10, which further comprises capacitive means (Cl to CM) coupled to said dummy word line.

Claim 14

A semiconductor memory device according to claim 11, wherein said capacitive means includes at least one MOS capacitor.

Claim 15

A semiconductor memory device according to claim 10 or 11, which further comprises decoding means (4) for selectively energizing said plurality of pairs of data lines and a pair of input/output lines (9-1, 9-2) coupled to said plurality of pairs of data lines through said decoding means.

Claim 16

A semiconductor memory device according to claim 13, wherein said sense amplifier means (400) includes a sense amplifier having input/output-terminals coupled to said input/output lines for amplifying a data signal on said input/output lines in response to an output signal from said energizing signal generating means.

Claim 17

A semiconductor memory device according to claim 10 or 11, which further comprises means (6) coupled to said plurality of pairs of data lines for setting said data lines to an equal potential level every time an address designating operation is effected.

Claim 18

A semiconductor memory device according to claim 10 or 11, wherein said sense amplifier means includes a plurality of sense amplifiers (SA-1 to SA-M) each having input/output terminals coupled to said plurality of pairs of data lines for amplifying a data signal on the corresponding pair of data lines in response to an output signal from said energizing signal generating means.

Claim 19

A semiconductor memory device according to claim 10 or 11, wherein said dummy word line (WD) is made practically of the same semiconductor material as that of said at least one word line.

Claim 20

A semiconductor memory device according to claim 10 or 11, wherein said dummy word line (W D ) extends substantially parallel to said word lines.

Claim 21

A semiconductor memory device according to claim 10 or 11, which further comprises decoding means (2) for selectively energizing said plurality of word lines, said decoding means (2) and said dummy selection signal generating means (20) having practically the same response time characteristics.

Claim 22

A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC-MN) arranged in a matrix array, a plurality of word lines (Wl to WN) each commonly connected to the semiconductor memory cells in each row of said matrix array, a plurality of data lines (D2-1 to D2-M, D3-1 to D3-M) for transferring data with respect to said semiconductor memory cells, at least one dummy word line (WDO, W D l), sense amplifier means (504) coupled to said plurality of data lines and to said at least one dummy data line for amplifying data transferred through said data lines and dummy data line, and energizing signal generating means (510) for producing an energizing signal for activating said sense amplifier means (504), characterized by: a dummy selection signal generating means (506, 508) for supplying a dummy selection signal to said energizing signal generating means (510) to cause said energizing signal generating means to produce an energizing signal every time an address designating operation is effected.

Claim 23

A semiconductor memory device comprising a plurality of semiconductor memory cells (MC-11 to MC-MN) arranged in a matrix array, a plurality of word lines (Wl to WN) each commonly connected to the semiconductor memory cells in each row of said matrix array, a plurality of data lines (D2-1 to D2-M, D3-1 to D3-M) for transferring data with respect to said semiconductor memory cells, at least one dummy word line (WDO, W D l), sense amplifier means (504) coupled to said plurality of data lines and to said at least one dummy data line for amplifying data transferred through said data lines and dummy data line, and energizing signal generating means (510) for producing an energizing signal for activating said sense amplifier means (504), characterized by: a dummy selection signal generating means (506, 508) for supplying a dummy selection signal to said energizing signal generating means (510) to cause said energizing signal generating means to produce an energizing signal every time an address designating operation is effected.

Claim 24

A semiconductor memory device according to claim 20, which further comprises at least one dummy data line coupled to said sense amplifier and at least one dummy memory cell coupled to said at least one dummy word line for supplying a dummy data to said dummy data line in response to an energizing signal supplied from said energizing signal generating means through said dummy word line.

Claim 25

A semiconductor memory device according to claim 20 or 21, wherein said dummy word line is made practically of the same semiconductor material as that of said word lines.

Claim 26

A semiconductor memory device according to claim 20 or 21, wherein said dummy word line extends substantially parallel to said word lines.

Claim 27

A semiconductor memory device according to claim 20 or 21, which further comprises decoding means for selectively energizing said plurality of word lines, said decoding means and said dummy selection signal generating means having practically the same response time characteristics.