Long write test

Claim 3

The method of claim 1, wherein before the step of writing to the plurality of bitlines, comprising the additional step of: disabling the plurality of wordlines within the selected portion of the static memory array.

Claim 4

The method of claim 2, wherein only one row address signal of the plurality of row address signals is overridden in a disabling state to ensure that the plurality of wordlines within the selected portion of the static memory array are disabled.

Claim 5

The method of claim 1, wherein during the test mode only a subset of the plurality of address signals are overridden.

Claim 6

The method of claim 1, wherein the plurality of bitlines are recovered in a first phase and a second phase.

Claim 7

The method of claim 5, wherein in the first phase, the plurality of bitlines are recovered to a first predetermined logic level.

Claim 8

The method of claim 6, wherein the first predetermined logic level is equal to Vcc-VTn, wherein Vcc is a power supply of the static memory device and VTn is an n-channel transistor threshold voltage.

Claim 9

The method of claim 6, wherein the plurality of bitlines are recovered to the first predetermined logic level by a plurality of write drivers.

Claim 10

The method of claim 5, wherein in the second phase, the plurality of bitlines are recovered to a second predetermined logic level.

Claim 11

The method of claim 9, wherein the plurality of bitlines are recovered to the second predetermined logic level by a plurality of corresponding bitline loads.

Claim 12

The method of claim 9, wherein the second predetermined logic level is equal to Vcc, wherein Vcc is a power supply of the static memory device.

Claim 13

The method of claim 1, wherein read disturbing the selected portion of the static memory device is accomplished by fast row cycling through the selected portion of the static memory device.

Claim 14

The method of claim 12, wherein the static memory device is a 1 Meg static random access memory (SRAM), the selected portion of the 1 Meg SRAM is a block having 512 wordlines representative of one sixteenth of the 1 Meg SRAM, and after fast row cycling through the block, the 512 wordlines of the block have been enabled and disabled in a 512 cycles.

Claim 15

The method of claim 1, wherein the predetermined period of time for which the plurality of bitlines are written is more than approximately 1 μS.

Claim 16

The method of claim 1, wherein static memory device is a 1 Meg static random access memory (SRAM) and the selected portion is a block representative of one sixteenth of the 1 Meg SRAM.

Claim 17

The method of claim 1, wherein selecting the portion of the static memory device to subject to a long write test is accomplished when a block select signal generated by block select circuitry is equal to a predetermined logic level.

Claim 18

The method of claim 16, wherein during the test mode, the block select signal controls a plurality of bitline loads.

Claim 19

The method of claim 17, wherein equilibration of the plurality of bitlines is disabled during the test mode.

Claim 20

The method of claim 1, wherein before the step of writing to the plurality of bitlines, comprising the additional step of: switching an address signal of the plurality of address signals from a first logic state to a second logic state, such that only a portion of the plurality of bitlines is written to simultaneously.

Claim 21

The method of claim 19, wherein only one-half of the plurality of bitlines is written to simultaneously.

Claim 24

The method of claim 21, wherein upon entering the long write test, the static memory device first enters the staggering condition and then transitions to the enabling condition.

Claim 25

The method of claim 21, wherein the static memory device transitions from the enabling condition to the staggering condition before exiting the long write test.

Claim 26

A structure to perform long write testing of a static memory device, comprising: a selected portion of a static memory device having a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals; and an address buffer circuit which controls the plurality of address signals to perform the long write testing of the static memory device, wherein the address buffer circuit comprises: an address bond pad having an address signal of the plurality of address signals; a first inverting element having the address signal as an input terminal and producing an output signal that is inverted with respect to the address signal, wherein the output signal of the first inverting element is an address complement signal produced by the address buffer circuit; a passgate, having the address complement signal as an input signal, controlled by a first address override signal and a second address override signal to selectively pass the address complement signal as an output signal, wherein when the first address override signal is a first logic level and the second address override signal is a second logic level, the selected portion of the static memory device is placed in a test mode; a pull-up element, having a first terminal electrically connected to a first supply voltage and a second terminal electrically connected to the output signal of the passgate, controlled by a first control signal; a pull-down element, having a first terminal electrically connected to the output signal of the passgate and a second terminal electrically connected to a second supply voltage, controlled by a second control signal; a second inverting element, having an input terminal electrically connected to a node comprised of the output signal of the passgate, the second terminal of the pull-up element, and the first terminal of the pull-down element, which produces an address true signal of the address buffer circuit; wherein the address complement signal is controlled by the address signal and the address true signal is controlled by the first control signal and the second control signal, such that when the first control signal is the second logic level the passgate is turned off and the address true signal is equal to the second logic level, and when the second control signal is the first logic level the passgate is turned off and the address true signal is equal to the first logic level.

Claim 27

A structure to perform long write testing of a static memory device, comprising: a selected portion of a static memory device having a plurality of wordlines, a plurality of bitlines, and a plurality of address signals, including a plurality of row address signals and a plurality of column address signals; and an address buffer circuit which controls the plurality of address signals to perform the long write testing of the static memory device, wherein the address buffer circuit comprises: an address bond pad having an address signal of the plurality of address signals; a first inverting element having the address signal as an input terminal and producing an output signal that is inverted with respect to the address signal, wherein the output signal of the first inverting element is an address complement signal produced by the address buffer circuit; a passgate, having the address complement signal as an input signal, controlled by a first address override signal and a second address override signal to selectively pass the address complement signal as an output signal, wherein when the first address override signal is a first logic level and the second address override signal is a second logic level, the selected portion of the static memory device is placed in a test mode; a pull-up element, having a first terminal electrically connected to a first supply voltage and a second terminal electrically connected to the output signal of the passgate, controlled by a first control signal; a pull-down element, having a first terminal electrically connected to the output signal of the passgate and a second terminal electrically connected to a second supply voltage, controlled by a second control signal; a second inverting element, having an input terminal electrically connected to a node comprised of the output signal of the passgate, the second terminal of the pull-up element, and the first terminal of the pull-down element, which produces an address true signal of the address buffer circuit; wherein the address complement signal is controlled by the address signal and the address true signal is controlled by the first control signal and the second control signal, such that when the first control signal is the second logic level the passgate is turned off and the address true signal is equal to the second logic level, and when the second control signal is the first logic level the passgate is turned off and the address true signal is equal to the first logic level.

Claim 28

The structure of claim 24, wherein the plurality of bitlines within the selected portion of the static memory device are written to simultaneously for a predetermined period of time, thereby defining a long write test of the selected portion of the static memory device, the plurality of bitlines within the selected portion of the static memory device are then recovered, and the selected portion of the static memory device is read disturbed.

Claim 29

The structure of claim 25, wherein before the plurality of bitlines within the selected portion of the static memory device are written to simultaneously for a predetermined period of time, the plurality of wordlines within the selected portion of the static memory array are disabled.

Claim 30

The structure of claim 26, wherein only one row address signal of the plurality of row address signals is overridden in a disabling state to ensure that the plurality of wordlines within the selected portion of the static memory array are disabled.

Claim 31

The structure of claim 25, wherein during the test mode only a subset of the plurality of address signals are overridden.

Claim 32

The structure of claim 25, wherein the plurality of bitlines are recovered in a first phase and a second phase.

Claim 33

The structure of claim 29, wherein in the first phase, the plurality of bitlines are recovered to a first predetermined logic level.

Claim 34

The structure of claim 30, wherein the first predetermined logic level is equal to Vcc-VTn, wherein Vcc is a power supply of the static memory device and VTn is an n-channel transistor threshold voltage.

Claim 35

The structure of claim 30, wherein the plurality of bitlines are recovered to the first predetermined logic level by a plurality of write drivers.

Claim 36

The structure of claim 29, wherein in the second phase, the plurality of bitlines are recovered to a second predetermined logic level.

Claim 37

The structure of claim 33, wherein the plurality of bitlines are recovered to the second predetermined logic level by a plurality of corresponding bitline loads.

Claim 38

The structure of claim 33, wherein the second predetermined logic level is equal to Vcc, wherein Vcc is a power supply of the static memory device.

Claim 39

The structure of claim 25, wherein the selected portion of the static memory device is read disturbed by fast row cycling through the selected portion of the static memory device.

Claim 40

The structure of claim 36, wherein the static memory device is a 1 Meg static random access memory (SRAM), the selected portion of the 1 Meg SRAM is a block having 512 wordlines representative of one sixteenth of the 1 Meg SRAM, and after fast row cycling through the block, the 512 wordlines of the block have been enabled and disabled in 512 cycles.

Claim 41

The structure of claim 25, wherein the predetermined period of time for which the plurality of bitlines are written is more than approximately 1 μS.

Claim 42

The structure of claim 25, wherein only a portion of the plurality of bitlines is written to simultaneously by switching the address signal from a first logic state to a second logic state.

Claim 43

The structure of claim 39, wherein only one-half of the plurality of bitlines is written to simultaneously.

Claim 44

The structure of claim 39, wherein when the address signal is equal to the first logic state, the address true signal of the address signal is equal to the first logic state and the address complement signal of the address signal is equal to the second logic state, thereby defining a staggering condition; when the address signal is equal to the second logic state, the address true signal and the address complement signal are both equal to the first logic state, thereby defining an enabling condition.

Claim 45

The structure of claim 41, wherein upon entering the long write test, the static memory device first enters the staggering condition and then transitions to the enabling condition.

Claim 46

The structure of claim 41, wherein the static memory device transitions from the enabling condition to the staggering condition before exiting the long write test.

Claim 47

The structure of claim 24, wherein static memory device is a 1 Meg static random access memory (SRAM) and the selected portion is a block representative of one sixteenth of the 1 Meg SRAM.

Claim 48

The structure of claim 24, wherein the portion of the static memory device is selected when a block select signal of a block select circuit is equal to a predetermined logic level.

Claim 49

The structure of claim 45, wherein during the test mode, the block select signal controls a plurality of bitline loads of the selected portion of the static memory device, wherein the plurality of bitline loads are electrically connected to the plurality of bitlines.

Claim 50

The structure of claim 46, wherein equilibration of the plurality of bitlines is disabled during the test mode.

Claim 51

The structure of claim 24, wherein the address buffer circuitry is a row address driver circuit.