Semiconductor memory with built-in parallel bit test mode

Claim 2

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks; plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality Of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines, on said associated plural pairs of data lines in write mode; and a test circuit for performing control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which are equal or greater in number than those DQ buffer circuits needed for normal reading/writing to... connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM and a symbol or a mark indicating a minimum possible refresh cycle is affixed on a package of said DRAM.

Claim 3

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks: plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines on said associated plural pairs of data lines in write mode; and a test circuit for performing control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which are equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM, and said semiconductor memory further comprises a circuit for programming a minimum possible refresh cycle in association with any external pin of said DRAM in such a way that contents of a program is detectable after sealing said DRAM in a package.

Claim 4

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks: plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines on said associated plural pairs of data lines in write mode; and a test circuit for performing control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which are equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM, and said semiconductor memory further comprises a circuit for programming a minimum possible refresh cycle in association with any external pin of said DRAM in such a way that contents of a program is detectable after sealing said DRAM in a package.

Claim 5

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks; plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines, on said associated plural pairs of data lines in write mode; and a test circuit for performing control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which are equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein in parallel bit test mode, said test circuit reduces driving power of a sense amplifier driver in normal mode.

Claim 6

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks; plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines, on said associated plural pairs of data lines in write mode; and a test circuit for performing control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which are equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein in parallel bit test mode, said test circuit reduces driving power of a sense amplifier driver in normal mode.

Claim 7

The semiconductor memory according to claim 3, wherein said individual circuits are incorporated in a DRAM; and a symbol or a mark indicating a minimum possible refresh cycle is affixed on a package of said DRAM.

Claim 8

The semiconductor memory according to claim 3, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM; and said semiconductor memory further comprises a circuit for programming a minimum possible refresh cycle in association with any external pin of said DRAM in such a way that contents of a program is detectable after sealing said DRAM in a package.

Claim 9

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks; plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines, on said associated plural pairs of data lines in write mode; and a test circuit for performing Control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which am equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein said test circuit enters said parallel bit test mode in a special entry cycle or by applying an electrical signal to pads on a memory chip area, thereby freely changing the number of bits to be simultaneously tested.

Claim 10

A semiconductor memory with a built-in parallel bit test mode, comprising: a memory cell array laid out as a plurality of blocks; plural pairs of data lines provided for each of said blocks; plural pairs of read/write lines commonly provided for and in a vicinity of each of said blocks; a plurality of DQ buffer circuits, respectively provided for said blocks, for each amplifying data output on said plural pairs of data lines from an associated one of said blocks and sending resultant amplified data onto those plural pairs of read/write lines which are associated with that block in read mode, and writing data, written on those associated plural pairs of read/write lines, on said associated plural pairs of data lines in write mode; and a test circuit for performing Control in such a way that, when a parallel bit test mode is designated, said test circuit enables those DQ buffer circuits which am equal or greater in number than those DQ buffer circuits needed for normal reading/writing to connect said associated plural pairs of read/write lines in wired-OR fashion and to read out results of computation of pieces of data equal to or greater in number than said plural pairs of read/write lines onto said plural pairs of read/write lines in read mode, and to write the same data on those plural pairs of data lines equal to or greater in number than said plural pairs of read/write lines, wherein said test circuit enters said parallel bit test mode in a special entry cycle or by applying an electrical signal to pads on a memory chip area, thereby freely changing the number of bits to be simultaneously tested.

Claim 11

The semiconductor memory according to claim 6, wherein in parallel bit test mode, said test circuit reduces driving power of a sense amplifier driver in normal mode.

Claim 12

The semiconductor memory according to claim 7, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM; and said semiconductor memory further comprises a circuit for programming a minimum possible refresh cycle in association with any external pin of said DRAM in such a way that contents of a program is detectable after sealing said DRAM in a package.

Claim 13

The semiconductor memory according to claim 8, wherein said special entry cycle is acknowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.

Claim 14

The semiconductor memory according to claim 7, wherein said special entry cycle is acknowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.

Claim 15

The semiconductor memory according to claim 7, wherein said individual circuits are incorporated in a DRAM; and a symbol or a mark indicating a minimum possible refresh cycle is affixed on a package of said DRAM.

Claim 16

The semiconductor memory according to claim 11, wherein said special entry cycle is acknowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.

Claim 17

The semiconductor memory according to claim 6, wherein said special entry cycle is ackowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.

Claim 18

The semiconductor memory according to claim 6, wherein said plurality of DQ buffer circuits and said test circuit are incorporated in a DRAM; and a symbol or a mark indicating a minimun, possible refresh cycle is affixed on a package of said DRAM.

Claim 19

The semiconductor memory according to claim 14, wherein said special entry cycle is acknowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.

Claim 20

The semiconductor memory according to claim 6, wherein said plurality of DO buffer circuits and said test circuit are incorporated in a DRAM; and said semiconductor memory further comprises a circuit for programming a minimum possible refresh cycle in association with any external pin of said DRAM in such a way that contents of a program is detectable after sealing said DRAM in a package.

Claim 21

The semiconductor memory according to claim 16, wherein said special entry cycle is acknowledged by means of a WCBR cycle accompanied with an entry of a predetermined signal.