US5265100A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory with improved test mode
Assignee: STMicroelectronics lnc USA
•
Filing: 1990-07-13
•
Granted: 1993-11-23
•
Expires: 2010-07-13
Abstract
Abstract An integrated circuit memory is disclosed which has a parallel test read mode. The memory includes comparators for comparing multiple data words, on a bit-by-bit basis, during the parallel read mode, with the result of the comparison used to enable or disable the output buffers. In test mode, in the event of a failed parallel test comparison, the comparator causes the output buffers to go into a high-impedance state; for a passing parallel test, the actual data state is presented by the output terminals The comparison circuitry is in parallel with the output data path, so that the output data path is not adversely affected by the test circuitry, and so that the access time in test mode is the same as the access time during normal operation (assuming a passing test). The technique may be adapted to wide parallel test schemes.
Inventors
- 👤 David C. McClure
- 👤 Thomas A. Coker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 20:11
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/28; G11C29/30; G11C29/34; G11C29/38
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
95 words
A method of parallel testing a plurality of memory locations in an integrated circuit, comprising: selecting a plurality of memory locations; comparing the contents of said selected memory locations; communicating the contents of a first one of the selected memory locations to an output buffer of the integrated circuit during said comparing step; and disabling the output buffer from presenting the communicated contents of the first one of the selected memory locations, responsive to the result of the comparing step indicating that the contents of the selected memory locations do not all match one another.
Claim 2
Independent Claim
95 words
A method of parallel testing a plurality of memory locations in an integrated circuit, comprising: selecting a plurality of memory locations; comparing the contents of said selected memory locations; communicating the contents of a first one of the selected memory locations to an output buffer of the integrated circuit during said comparing step; and disabling the output buffer from presenting the communicated contents of the first one of the selected memory locations, responsive to the result of the comparing step indicating that the contents of the selected memory locations do not all match one another.
Claim 3
Dependent Claim
48 words
The method of claim 1, wherein said comparing step comprises: comparing first and second ones of said memory locations with one another; comparing third and fourth ones of said memory locations with one another; and comparing said second and third ones of sad memory locations with one another.
Claim 4
Dependent Claim
60 words
The method of claim 2, wherein said selecting step comprises: selecting a plurality of memory cells according to a portion of a column address so that the contents of said memory cells are communicated to local data buses; and wherein said local data buses each comprise a plurality of data lines, each for communicating the contents of a memory cell.
Claim 5
Dependent Claim
27 words
The method of claim 3, wherein said selecting step selects a plurality of data words; and wherein each of said data words comprises a plurality of bits.
Claim 6
Dependent Claim
64 words
The method of claim 4, wherein the number of data lines of said local data buses equals the number of bits in said data words; wherein the number of local data buses is greater than the number of selected data words; and wherein said selecting step further comprises: selecting a comparator from a plurality of comparators, corresponding to the number of data words selected.
References Cited (Backward Citations)
US4744061A
Cited
US4654849A
Cited
US4654849B1
Cited
US4860259A
Cited
US4873669A
Cited
US4896322A
Cited
EP0313040A2
Cited
US5060230A
Cited
US5075892A
Cited
US5072137A
Cited
US5072138A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-11-22 | 1997-05-24 | 1997-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-11-22 | 2001-05-24 | 2001-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-11-22 | 2005-05-24 | 2005-11-23 | $7700.00 | Window Closed / Lapsed |