Erasable programmable read only memory device

Claim 1

An erasable programmable read only memory device capable of being shifted into an operation selected from the group of a write-in mode of operation, a read-out mode of operation and a diagnostic mode of operation, comprising: a) a plurality of memory cell arrays each having a plurality of memory cells arranged in memory cell rows and memory cell columns, each of said memory cells being capable of memorizing a data bit in a rewritable and non-volatile manner; b) at least one redundant memory cell array having a plurality of redundant memory cells arranged in redundant memory cell rows and redundant memory cell columns, each of said memory cells being capable of memorizing a data bit in the rewritable and non-volatile manner, said memory cell columns being replacable with said redundant memory cell columns, respectively; c) a plurality of first write-in circuits each provided in association with each of said memory cell arrays and operative to write a data bit into a memory cell selected from the memory cell array; d) at least one second write-in circuit provided in association with said redundant memory cell array and operative to write a data bit into a redundant memory cell selected from the redundant memory cell array; e) a plurality of first sense amplifier circuits each provided in association with each of said memory cell arrays and operative to quickly decide the logic level of said data bit read out from the memory cell selected from the memory cell array; f) at least one second sense amplifier circuit provided in association with said redundant memory cell array and operative to quickly decide the logic level of said data bit read out from the memory cell selected from the redundant memory cell array; g) a plurality of first column selecting circuits each provided in association with each of said memory cell arrays and operative to provide a data path between one of said memory cell columns selected from the memory cell array and one of each first write-in circuit and each first sense amplifier circuit depending upon the operation to which said erasable programmable read only memory device is shifted; h) at least one second column selecting circuit provided in association with said redundant memory cell array and operative to provide a data path between one of said redundant memory cell columns selected from the redundant memory cell array and one of said second write-in circuit and said second sense amplifier circuit depending upon the operation to which said erasable programmable read only memory device is shifted; i) programmble link means operative to memorize a replacement between said memory cell columns and said redundant memory cell columns and providing a replacing information; j) a control circuit operative to compare the memory cell column selected from said memory cell columns with said memory cell column replaced with said redundant memory cell column on the basis of said replacing information and produce a multi-bit control signal if these memory cell columns are identical with each other; k) a plurality of input/output data buffer circuits each provided in association with each of said memory cell arrays and operative to temporally store the data bit read out from or written into the memory cell selected from said memory cell array; 1) a plurality of output data selecting circuits each provided in association with each of said memory cell arrays and activated in said read-­out mode of operation, each of said output data selecting circuits being operative to transfer the data bit read out from the memory cell selected from said memory cell array in the absence of said multi-bit control signal but transfer the data bit read out from the redundant memory cell selected from said redundant memory cell array in the presence of said multi-bit control signal; and m) a plurality of input data distributing circuits each provided in association with each of said memory cell arrays and activated in said write-in mode of operation and said diagnostic mode of operation, each of said input data distributing circuits being operative to transfer the data bit stored in each input/output data buffer circuit to said first write-in circuit in the absence of said multi-bit control signal but transfer the data bit to the second write-in circuit when the erasable programmable read only memory device is shifted into the write-in mode of operation, characterized by a mode signal producing circuit operative to produce a mode signal representative of said diagnostic mode of operation which causes at least one of said input data distributing circuits to transfer the data bit stored in said input/output data buffer circuit to both of said first and second write-in circuits.