Circuit configuration and a method for the testing of storage cells

Claim 2

Circuit configuration for testing storage cells disposed in a matrix in a semiconductor memory including word and bit lines for driving the storage cells, and evaluator circuits each being assigned to a respective bit line and each dividing the respective bit line into two identical first and second bit line halves, comprising: a pair of first and second fault lines, a precharging device connected to said pair of fault lines, a comparator circuit having inputs connected to said pair of fault lines and an outlet issuing an output signal indicating the occurrence of faults in test operation, first and second switching transistors having sources, drains and gates, the gates of said first switching transistors each being connected to a respective one of said first bit line halves of said bit lines, and the gates of said second switching transistors each being connected to a respective one of said second bit line halves of said bit lines, the sources of all of said switching transistors being commonly connected to a potential corresponding to one of two mutually-complementary logic levels carried by said pair of fault lines in test operation, the drains of said second switching transistors being connected to said first fault line, and the drains of said first switching transistors being connected to said second fault line.

Claim 3

Circuit configuration according to claim 1, wherein said potential connected to the source of each of said switching transistors is equal to a reference potential of the circuit configuration.

Claim 4

Circuit configuration according to claim 1, wherein the potential connected to the source of each of said switching transistors is equal to a supply potential of the circuit configuration.

Claim 5

Circuit configuration according to claim 1, wherein said precharging device includes an RS flip-flop circuit having two mutually-complementary outputs, and further switching transistors connected between said outputs of said RS flip-flop circuit and said pair of fault lines.

Claim 6

Circuit configuration according to claim 1, wherein said comparator circuit is an XOR-circuit.

Claim 7

Circuit configuration according to claims 1, wherein said comparator circuit is an XNOR-circuit.

Claim 8

Method of testing storage cells disposed in a matrix in a semiconductor memory including word lines and bit lines for driving the storage cells, and evaluator circuits each dividing a respective one of the bit lines into two identical bit line halves, which comprises: charging all of the storage cells connected to a word line to an equal logic level in test operation; precharging a pair of fault lines to two mutually-complementary logic levels being identical with respect to their significance to logic levels which can be input into the storage cells in the form of electric charges; activating a word line for transferring a charge stored in the storage cells connected to the word line to the respective associated bit line halves; evaluating and amplifying the read-out charges with the evaluator circuits, and forming logic levels assigned to the read-out charges; driving and switching switching means connected between the bit line halves and the fault lines into conductivity or blocking with the logic levels; retaining the logic state of the two fault lines or changing the logic state of one of the fault lines depending upon the switching characteristics of the switching means; and checking whether or not the fault lines retain the mutually-complementary logic levels impressed by the precharging step upon read-out and evaluation of the charges of the storage cells with a comparator circuit connected to the fault lines.

Claim 9

Method of testing storage cells disposed in a matrix in a semiconductor memory including word lines and bit lines for driving the storage cells, and evaluator circuits each dividing a respective one of the bit lines into two identical bit line halves, which comprises: charging all of the storage cells connected to a word line to an equal logic level in test operation; precharging a pair of fault lines to two mutually-complementary logic levels being identical with respect to their significance to logic levels which can be input into the storage cells in the form of electric charges; activating a word line for transferring a charge stored in the storage cells connected to the word line to the respective associated bit line halves; evaluating and amplifying the read-out charges with the evaluator circuits, and forming logic levels assigned to the read-out charges; driving and switching switching means connected between the bit line halves and the fault lines into conductivity or blocking with the logic levels; retaining the logic state of the two fault lines or changing the logic state of one of the fault lines depending upon the switching characteristics of the switching means; and checking whether or not the fault lines retain the mutually-complementary logic levels impressed by the precharging step upon read-out and evaluation of the charges of the storage cells with a comparator circuit connected to the fault lines.

Claim 10

Method according to claim 7, which comprises carrying out the precharging step by precharging outputs of an RS flip-flop connected to the fault lines through further switching means, and subsequently disconnecting the outputs of the RS flip-flop from the fault lines with the further switching means.

Claim 11

Method according to claim 7, which comprises carrying out the checking step with an XOR-circuit forming the comparator circuit.

Claim 12

Method according to claim 7, which comprises carrying out the checking step with an XNOR-circuit forming the comparator circuit.

Claim 13

Method according to claim 7, which comprises assigning the logic levels to the two fault lines in such a way that the fault line connected through the switching means to the storage cells to be tested in a test cycle has a logic level complementary to the logic level assigned to the storage cells which are to be tested in the form of stored charges, in the case of "no fault".

Claim 14

Method according to claim 7, which comprises assigning the logic levels to the two fault lines in such a way that the fault line connected through the switching means to the storage cells to be tested in a test case has a logic level equal to the logic level assigned to the storage cells which are to be tested in the form of stored charges, in the case of "no fault".