EP0143624A2
Expired / Lapsed
EP
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Dynamic semiconductor memory device having divided memory cell blocks
Assignee: Fujitsu Ltd
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Filing: 1984-11-23
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Granted: —
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Expires: 2004-11-23
Abstract
Abstract In a dynamic semiconductor memory device comprising memory cells divided into a plurality of blocks (1-1, 1-2), selectively operable simultaneous write enable circuitry (TP1, R3, Q31, Q31-Q34) performs a write operation simultaneously upon the plurality of blocks, and comparison circuitry (Q35-Q38, R4, R5) compares read data of one block with read data of the other block, thereby carrying out a test more rapidly than is possible with an otherwise comparable prior art device.
Inventors
- 👤 Yoshihiro Takemae
- 👤 Kimiaki Sato
- 👤 Masao Nakano
- 👤 Tomio Nakano
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 10:28
CPC Classifications
G; G11; G11C; G11C29/00; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/1666; G06F11/167; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C19/00; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/26; G11C29/70
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
196 words
A dynamic semiconductor memory device comprising a plurality of separate blocks (1-1, 1-2) of memory cells, which blocks are provided with respective write circuits (3-1, 3-2) for writing data into those blocks, and with respective data output circuits (4-1, 4-2) for storing data read out from those blocks, which data output circuits have respective "true" output signal lines (D 1 ,D 2 ) and respective "complementary" output signal lines ( D 1 , D 2 ) ; characterised in that selectively operable simultaneous write enable circuitry (TPl, R 3 , Q 31 -Q 34 ) is connected to the said write circuits (3-1, 3-2) for causing respective write operations to be performed thereby simultaneously upon the said blocks (1-1, 1-2) of memory cells, the said "true" output signal lines (D 1 , D 2 ) are connected to drive first output circuitry (Q 35 , Q 37' TB, R 4 , TP2),for providing a first logic level output, and the said "complementary" output signal lines ( D 1 , D 2 ) are connected to drive second output circuitry (Q 36 , Q 38 , TB, R 5 , TP3),for providing a second logic level output.
Claim 2
Dependent Claim
196 words
A dynamic semiconductor memory device comprising a plurality of separate blocks (1-1, 1-2) of memory cells, which blocks are provided with respective write circuits (3-1, 3-2) for writing data into those blocks, and with respective data output circuits (4-1, 4-2) for storing data read out from those blocks, which data output circuits have respective "true" output signal lines (D 1 ,D 2 ) and respective "complementary" output signal lines ( D 1 , D 2 ) ; characterised in that selectively operable simultaneous write enable circuitry (TPl, R 3 , Q 31 -Q 34 ) is connected to the said write circuits (3-1, 3-2) for causing respective write operations to be performed thereby simultaneously upon the said blocks (1-1, 1-2) of memory cells, the said "true" output signal lines (D 1 , D 2 ) are connected to drive first output circuitry (Q 35 , Q 37' TB, R 4 , TP2),for providing a first logic level output, and the said "complementary" output signal lines ( D 1 , D 2 ) are connected to drive second output circuitry (Q 36 , Q 38 , TB, R 5 , TP3),for providing a second logic level output.
Claim 3
Dependent Claim
150 words
A device as claimed in claim 1, including a data input buffer (2) for deriving from a primary input data signal ( T D in ), of a TTL level, a first MOS-level data signal (D. ) and a second MOS-level data signal ( D in ) which is the inverse of the first, a first plurality of transfer gate components (Q 1 , Q 3 ) which are actuable by respective address signals (A , A o ) and are connected for delivering the said first MOS-level data signal (D. ) respectively to the said write circuits (3-1, 3-2), and a second plurality of transfer gate components (Q 2 , Q 4 ) which are actuable respectively by the said address signals (A , A o ) and are connected for delivering the said second MOS-level data signal ( D in ) to the said write circuits (3-1, 3-2).
Claim 4
Dependent Claim
102 words
A device as claimed in claim 2, wherein the said simultaneous write enable circuitry comprises first auxiliary transfer gate means (Q 31 , Q 33 ) ' connected in parallel with the said first plurality of transfer gate components (Q 1 , Q 3 ), second auxiliary transfer gate means (Q 32 , Q 34 ) ' connected in parallel with the said second plurality of transfer gate components (Q , Q 4 ), and selectively operable actuating means (TP1, R ) connected with the said first and second auxiliary transfer gate means (Q 31 -Q 34 ) for actuating them simultaneously.
Claim 5
Dependent Claim
60 words
A device as claimed in claim 3, wherein the said selectively operable actuating means comprises pulling-down means (R 3 ) connected to a test pad (TPl) which is connected to the said first and second transfer gate means (Q 31 -Q 34 ) so that an actuating potential can be applied thereto by way of the said test pad (TPl).
Claim 6
Dependent Claim
167 words
A device as claimed in claim 1, including a data input buffer (2) for receiving an input data signal ( T D in ) of a TTL level and generating an input data signal (D. ) of a MOS level and its inverted signal ( D in ) ; and a plurality of transfer gate means (Q 1 -Q 4 ), each linked between said data input buffer (2) and one of said write circuits (3-1, 3-2); wherein said simultaneous write enable circuitry comprises a test pad (TP1'); a pulling-down means (R 3 ) connected to said test pad (TP1') ; and a plurality of NAND gate means (Q 51 -Q 53 , Q 54 -Q 56 ), each having an input connected to said test pad (TP1'), an input for receiving the respective one (A 0 , A 0 ) of address signals, and an output connected to one of said transfer gate means (Q1-Q4), thereby activating said transfer gate means (Q 1 -Q 4 ).
Claim 7
Independent Claim
136 words
A device as claimed in any preceding claim, including first and second power supply terminals (V CC' GND), wherein said first and second output circuitry comprises: a pair of test pads (TP2, TP3); a plurality of pairs of pulling-up means (R 4 , R 5 ), each pair connected to one of said test pads (TP2, TP3) and to said first power supply terminal (V CC ) ; and a plurality of pairs of transfer gate means (Q 35 -Q 38 ), each pair connected to said test pads (TP2, TP3) and to said second power supply terminal (GND), each pair of said transfer gate means (Q 35 -Q 38 ) being controlled by each read data (D 1 , D 1 , D 2 , D 2 ) of said data output circuits (4-1, 4-2).
Claim 8
Independent Claim
133 words
A device as claimed in any one of claims 1 to 5, wherein said first and second output circuitry comprises a pair of test pads (TP2', TP3'); a plurality of pairs of pulling-up means (R 4 , R5), each pair connected to one of said test pads (TP2', TP3') and to said first power supply terminal (V CC ) ; and a plurality of transfer gate means, each connected to one of said test pads (TP2', TP3') and to said second power supply terminal (GND), each of said transfer gate means comprising a plurality of gates (Q 61 -Q 64 ) in series, each of said gates being controlled by one of read data (D 1 , D 1 , D 2 , D 2 ) of said data output circuits (4-1, 4-2).
Claim 9
Independent Claim
166 words
A device as claimed in any one of claims 1 to 5, including first and second power supply terminals (V CC , GND), wherein said first and second output circuitry comprises a pair of test pads (TP2, TP3); a plurality of pairs of pulling-up means (R 4 , R5), each pair connected to one of said test pads (TP2, TP3) and to said first power supply terminal (V CC ) ; a plurality of pairs of transfer gate means (Q 81 -Q 84 , Q 86 -Q 89 ), each pair of said transfer gate means being connected to said test pads (TP2, TP3) and being controlled by each read data (D 1 , D 1 , D 2 , D 2 ) of said data output circuits (4-1, 4-2); and a plurality of means, connected to said transfer gate means (Q 81 -Q 84 , Q 86 -Q 89 ) and to said second power supply terminal (GND), for selectively activating said transfer gate means.
Claim 10
Dependent Claim
36 words
A device as claimed in claim 8, wherein each of said selectively activating means comprises a test pad (TP4, TP5) and a pulling-down means (R 6 , R7 ) connected to that test pad (TP4, TP5).
Claim 11
Dependent Claim
25 words
A device as claimed in claim 4,5,6,7,8 or 9, wherein each test pad is connected to a pad for use in a normal operation mode.
Claim 12
Independent Claim
86 words
A device as claimed in any preceding claim, wherein the said first and second output circuitry includes a pair of data output buses (DO, DO), and a data output buffer (Q 11 , Q 12 ) connected to said data output buses (DO, DO ) ; and wherein the connections are such that all the read data (D 1 , D 1 , D 2 , D 2 ) of said data output circuits (4-1, 4-2) is transmitted simultaneously to said data output buses (DO, DO).
References Cited (Backward Citations)
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