Parallel read circuit for testing high density memories

Claim 1

A parallel read circuit for testing high density memories, comprising: a plurality of cell array blocks activated simultaneously during a read cycle; a plurality of input/output lines connected with said respective cell array blocks, for transmitting a predetermined test pattern to said cell array blocks during a write cycle and transmitting cell data read out from said cell array blocks in response to said predetermined test pattern during said read cycle; a plurality of data buses, one each for a corresponding one of said cell array blocks, for bussing said cell data loaded on a selected one of said input/output data lines; a data bus comparator for comparing data loaded on said data buses to generate a test output; a common output buffer for buffering commonly the respective data loaded on said data buses during a normal mode and said test output during a test mode; a plurality of individual data line sense amplifiers coupled to corresponding ones of said input/output data lines, said sense amplifiers amplifying respective said cell data loaded on said corresponding ones of said input/output data lines during said test mode; and a plurality of data line comparators, one each for a corresponding one of said cell array blocks, for comparing said amplified data from said sense amplifiers per each separate cell array block to form primarily compared data to be sent to a corresponding one of said data buses.