Integrated circuit memory with disabled edge transition pulse generation during special test mode

Claim 2

An integrated memory circuit, having a normal operating mode and a special test mode, comprising: a plurality of memory cells, arranged in rows and columns; a plurality of input terminals; circuitry for selecting one of said plurality of memory cells responsive to an address signal received at said plurality of input terminals; edge transition detection circuitry, coupled to said plurality of input terminals, for initiating a memory operation responsive to detecting a logic transition at said plurality of input terminals; test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; and a gating circuit, coupled to said test mode enable circuitry and to the edge transition detection circuitry, for inhibiting said edge transition detection circuitry from initiating the memory operation responsive to said test mode enable signal.

Claim 3

The circuit of claim 1, wherein said plurality of input terminals comprise: a plurality of address terminals, for receiving the address signal; a plurality of data terminals; and a control terminal.

Claim 4

The circuit of claim 2, wherein said edge transition detection circuitry is coupled to said plurality of address terminals, and initiates the memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals.

Claim 5

An integrated memory circuit, having a normal operating mode and a special test mode, comprising: a plurality of memory cells, arranged in rows and columns; a plurality of address terminals, for receiving an address signal; a plurality of data terminals; a control terminal; circuitry for selecting one of said plurality of memory cells responsive to the address signal received at said plurality of address terminals; edge transition detection circuitry, coupled to said plurality of address terminals and to said plurality of data terminals, for initiating a memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or data terminals; and test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; wherein said edge transition detection circuitry is coupled to said test mode enable circuitry to receive the test mode enable signal, so that said edge transition detection circuitry is inhibited from initiating the memory operation responsive to said test mode enable signal.

Claim 6

An integrated memory circuit, having a normal operating mode and a special test mode, comprising: a plurality of memory cells, arranged in rows and columns; a plurality of address terminals, for receiving an address signal; a plurality of data terminals; a control terminal; circuitry for selecting one of said plurality of memory cells responsive to the address signal received at said plurality of address terminals; edge transition detection circuitry, coupled to said plurality of address terminals and to said plurality of data terminals, for initiating a memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or data terminals; and test mode enable circuitry for generating a test mode enable signal responsive to receiving a test mode select signal; wherein said edge transition detection circuitry is coupled to said test mode enable circuitry to receive the test mode enable signal, so that said edge transition detection circuitry is inhibited from initiating the memory operation responsive to said test mode enable signal.

Claim 7

The circuit of claim 3, wherein said edge transition detection circuitry is also coupled to said control terminal, and initiates a memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or at said control terminal.

Claim 8

The circuit of claim 1, wherein each column of memory cells is associated with a pair of bit lines; and wherein, during the special test mode, a differential voltage is placed across at least one of the pair of bit lines; and further comprising: an equilibration transistor, having a conduction path connected between the bit lines in each pair of bit lines, and having a control terminal controlled in such a manner as to turn on the equilibration transistor responsive to initiation of a memory operation by said edge transition detection circuitry.

Claim 9

The circuit of claim 6, wherein said special test mode corresponds to a stress test; and further comprising: a power supply terminal, for receiving a power supply voltage near a first voltage in the normal operating mode, and for receiving a power supply voltage near a second, higher, voltage for the stress test.

Claim 10

The circuit of claim 1, wherein the test mode select signal comprises an overvoltage signal at one of said plurality of input terminals.

Claim 11

The circuit of claim 8, wherein the memory has a plurality of special test modes; and wherein one of the plurality of special test modes is selected responsive to a code received in conjunction with the overvoltage signal.

Claim 14

The method of claim 10, wherein said step of initiating a memory operation comprises generating an edge transition detection signal with a logic function responsive to detecting a logic level transition at one of the plurality of input terminals; wherein said step of initiating the special test mode comprises generating a test mode enable signal responsive to receiving the test mode enable signal; and wherein said inhibiting step comprises applying the test mode enable signal to the logic function so as to inhibit the logic function from generating the edge transition detection signal.

Claim 15

The method of claim 10, wherein the plurality of input terminals monitored in the monitoring step comprise address terminals.

Claim 18

The method of claim 10, wherein the memory comprises a plurality of memory cells arranged in rows and columns, each column of memory cells associated with one of a plurality of pairs of differential bit lines; and wherein said step of initiating a memory operation comprises precharging each of the differential bit lines to a power supply voltage.

Claim 19

The method of claim 10, wherein the memory comprises a plurality of memory cells arranged in rows and columns, each column of memory cells associated with one of a plurality of pairs of differential bit lines; and wherein said step of initiating the memory operation comprises equilibrating each of the pairs of differential bit lines.

Claim 20

The method of claim 15, wherein said step of initiating the special test mode comprises driving a differential voltage across at least one of the pairs of differential bit lines.

Claim 21

The method of claim 16, wherein said step of initiating the special test mode comprises driving a differential voltage across all of the pairs of differential bit lines.

Claim 22

The method of claim 10, further comprising: receiving a power supply at a power supply terminal at a first voltage during the normal operating mode, and at a second, elevated, voltage during the special test mode.

Claim 23

The method of claim 18, wherein the memory comprises a plurality of memory cells arranged in rows and columns, each column of memory cells associated with one of a plurality of pairs of differential bit lines; wherein said step of initiating the memory operation comprises equilibrating each of the pairs of differential bit lines; and wherein said step of initiating the special test mode comprises driving a differential voltage across at least one of the pairs of differential bit lines.

Claim 24

The method of claim 10, further comprising: powering up the memory during said step of initiating the special test mode.

Claim 25

The circuit of claim 3, wherein said edge transition detection circuitry is also coupled to said plurality of data terminals, and initiates the memory operation responsive to detecting a logic transition at one or more of said plurality of address terminals or at one or more of said data terminals.