Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a data line pair, a plurality of bit lie pairs each corresponding to a specific column, a plurality of word lines each corresponding to a specific row, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for generating an output pulse signal in response to any change in a column address signal or a row address signal, and a column address decoder circuit for generating a selecting signal to select one of said column switch circuits in accordance with said column address signal, each memory cell being connected to one of said bit line paris and to one of said word lines, one of said word lines being selected in accordance with said row address signal, said column switch circuit selected by said selecting signal being activated when said output pulse signal is in an active state, so that said selected column switch circuit is both activated for a predetermined period and is disabled after said predetermined period at least when said row address signal changes.

Claim 3

A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a data line pair, a plurality of bit lien pairs each corresponding to a specific column, a plurality of word lines each corresponding to a specific row, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit line pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuit for electrically charging said data line pair, an address transition detecting circuit for detecting any change in a row address signal or a column address signal to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal in order to selectively control each of said column switch circuit in accordance with said column address signal, each memory cell being connected to one of said bit line pairs and to one of said word lines, one of said words lines being selected in accordance with said row address signal, said column address decoder circuit outputting said selecting signal in accordance with a decoding signal of a column address bit and a predetermined one of said control pulse signals, so that a selected said column switch circuit is both activated for a predetermined period and is disabled after said predetermined period if at least said row address signal changes.

Claim 4

A semiconductor memory device comprising a plurality of memory cells disposed in the form of a matrix, a data line pair, a plurality of bit lien pairs each corresponding to a specific column, a plurality of word lines each corresponding to a specific row, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit line pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuit for electrically charging said data line pair, an address transition detecting circuit for detecting any change in a row address signal or a column address signal to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal in order to selectively control each of said column switch circuit in accordance with said column address signal, each memory cell being connected to one of said bit line pairs and to one of said word lines, one of said words lines being selected in accordance with said row address signal, said column address decoder circuit outputting said selecting signal in accordance with a decoding signal of a column address bit and a predetermined one of said control pulse signals, so that a selected said column switch circuit is both activated for a predetermined period and is disabled after said predetermined period if at least said row address signal changes.

Claim 5

A semiconductor memory device as set forth in claim 2, wherein said each column switch circuit includes a differential amplifier which uses said corresponding bit line pair as the input ad said data line pair as the output.

Claim 6

A semiconductor memory device as set forth in claim 2, wherein said each column switch circuit comprises first and second transistors provided between each line of said data line pair and a common node so that each transistor may be gate controlled by each line of said corresponding bit line pair and a third transistor provided between said common node and a discharging position so that said third transistor is gate-controlled by said selecting signal.

Claim 7

A semiconductor memory device as set forth in claim 4, wherein any of said first, second and third transistors is an N-channel MOS field effect transistor.

Claim 8

A semiconductor memory device comprising a plurality of memory cells disposed int he form of a matrix, a data line pair, a plurality of bit line pairs each corresponding to a specific column, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for detecting an address change to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal in order to selectively control each of said column switch circuits, each memory cell being connected to one of said bit line pairs, said column address decoder circuit outputting said selecting signal in accordance with a decoding signal of a column address bit and a predetermined one of said control pulse signals, said each column switch circuit comprising first and second transistors provided between each line of said data line pair and a common node so that said first and second transistors may be gate-controlled by each line of said corresponding bit line pair, and a third transistor provided between said common node and a discharging point so that said third transistor is gate-controlled by said selecting signal, and said predetermined control pulse signal being output from said address transition detecting circuit prior to a pulse signal to interrupt the operation of said precharger circuits.

Claim 9

A semiconductor memory device comprising a plurality of memory cells disposed int he form of a matrix, a data line pair, a plurality of bit line pairs each corresponding to a specific column, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for detecting an address change to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal in order to selectively control each of said column switch circuits, each memory cell being connected to one of said bit line pairs, said column address decoder circuit outputting said selecting signal in accordance with a decoding signal of a column address bit and a predetermined one of said control pulse signals, said each column switch circuit comprising first and second transistors provided between each line of said data line pair and a common node so that said first and second transistors may be gate-controlled by each line of said corresponding bit line pair, and a third transistor provided between said common node and a discharging point so that said third transistor is gate-controlled by said selecting signal, and said predetermined control pulse signal being output from said address transition detecting circuit prior to a pulse signal to interrupt the operation of said precharger circuits.

Claim 10

A semiconductor memory device comprising a plurality of memory cells disposed int he form of a matrix, a data line pair, a plurality of bit lien pairs each corresponding to a specific column, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for detecting an address change to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal based on a decoding signal of a column address bit in order to selectively control each of said column switch circuits, each memory cell being connected to one of said bit line pairs, characterized in that said each column switch circuit comprises first and second transistors provided between each line of said data line pair and a common node so that said transistors are gate-controlled by each line of said corresponding bit lien pair and a third and fourth transistors connected in series between said common node and a discharging point, one of said third and fourth transistors being gate-controlled by said selecting signal, the other of said third and fourth transistors being gage-controlled by a predetermined one of said control pulse signals.

Claim 11

A semiconductor memory device comprising a plurality of memory cells disposed int he form of a matrix, a data line pair, a plurality of bit lien pairs each corresponding to a specific column, a plurality of column switch circuits each provided for each of said bit line pairs with their one end connected to a corresponding bit lien pair and their other end connected to said data line pair for changing the potential difference between the lines of said data line pair according to the potential difference between the lines of said corresponding bit line pair when a selecting signal is entered, a plurality of precharger circuits for electrically charging said data line pair, an address transition detecting circuit for detecting an address change to sequentially generate control pulse signals, and a column address decoder circuit for generating said selecting signal based on a decoding signal of a column address bit in order to selectively control each of said column switch circuits, each memory cell being connected to one of said bit line pairs, characterized in that said each column switch circuit comprises first and second transistors provided between each line of said data line pair and a common node so that said transistors are gate-controlled by each line of said corresponding bit lien pair and a third and fourth transistors connected in series between said common node and a discharging point, one of said third and fourth transistors being gate-controlled by said selecting signal, the other of said third and fourth transistors being gage-controlled by a predetermined one of said control pulse signals.

Claim 12

A semiconductor memory device as set forth in claim 7 wherein any of said first, second, third and fourth transistors is an N-channel MOS field effect transistor.

Claim 13

A semiconductor memory device as set forth in claim 8 wherein said predetermined control pulse signal is outputted from said address transition detecting circuit in substantial synchronism with a control pulse signal to interrupt the operation of said precharger circuit emitted.