Compensating delay element for clock generation in a memory device

Claim 2

A delay circuit in an integrated circuit memory of the type having a plurality of memory cells, each memory cell comprising cross-coupled inverters connectable to differential bit lines by way of pass transistors controlled by a word line signal, each of the cross-coupled inverters comprising a drive transistor and a load; wherein the delay circuit is for generating an output clock signal responsive to an input clock signal, delayed in a manner corresponding to the response of the memory cell when accessed, and comprises: a first transistor, having a size corresponding to one of the pass transistors, having a gate for receiving the input clock signal, and having a source-drain path coupled on one side to an output node; a second transistor, having a size corresponding to one of the drive transistors, having a gate, and having a source-drain path coupled between a second side of the source-drain path of the first transistor and a reference voltage; and a bias circuit, having an output coupled to the gate of the second transistor, for generating a voltage corresponding to a high level voltage in the memory cell.

Claim 3

The delay circuit of claim 1, further comprising: a capacitive load coupled to the output node, having a capacitance modeling a load of one of the bit lines.

Claim 4

The delay circuit of claim 1, further comprising: a pull-up transistor, having a source-drain path coupled between the output node and a power supply voltage, and having a gate coupled to receive the input clock signal, for biasing the output node toward the power supply voltage responsive to the input clock signal being in an inactive state.

Claim 5

The delay circuit of claim 1, wherein said bias circuit comprises: a model bit line load, coupled on one side to a power supply voltage; and a third transistor, having a source-drain path coupled between the model bit line load and the output of the bias circuit, and having a gate biased to a voltage such that said third transistor is conductive, said third transistor having a size corresponding to one of the pass transistors.

Claim 6

The delay circuit of claim 4, further comprising: a low load, coupled between the output of the bias circuit and a reference voltage.

Claim 7

The delay circuit of claim 4, wherein the memory includes bit line loads coupled to bit lines therein; and wherein said model bit line load comprises: a transistor, having a conductivity type and size corresponding to a bit line load to which the bit line in the memory is coupled.

Claim 8

The delay circuit of claim 4, further comprising: an isolate transistor, having a source-drain path coupled in series with said model bit line load between the output of said bias circuit and the power supply voltage, and having a gate for receiving a select signal which, when inactive, makes said isolate transistor non-conductive.

Claim 9

The delay circuit of claim 7, further comprising: a discharge transistor, having a source-drain path coupled between the output of said bias circuit and a reference voltage, and having a gate for receiving the select signal which, when inactive, makes said discharge transistor conductive.

Claim 10

The circuit of claim 1, wherein the output clock signal of the delay circuit controls a sense amplifier in the integrated circuit memory.

Claim 11

The circuit of claim 1, wherein the memory cell high level voltage corresponds to a power supply voltage less the threshold voltage of one of the pass transistors.

Claim 12

In an integrated circuit memory of the type having a plurality of memory cells, each comprising cross-coupled inverters connectable to differential bit lines by way of pass transistors controlled by a word line signal, each of the cross-coupled inverters comprising a drive transistor and a load, a delay circuit for generating an output clock signal responsive to an input clock signal, delayed in a manner corresponding to the response of the memory cell when accessed, comprising: a first transistor, having a size corresponding to one of the pass transistors, having a gate for receiving the input clock signal, and having a source-drain path coupled on one side to an output node; a second transistor, having a size corresponding to one of the drive transistors, having a gate, and having a source-drain path coupled between a second side of the source-drain path of the first transistor and a reference voltage; and a bias circuit, having an output coupled to the gate of the second transistor, for generating a voltage corresponding to a high level voltage in the memory cell, comprising: a model bit line load transistor, having a source-drain path coupled between a power supply voltage and an intermediate node, and having a gate coupled to receive the input clock signal in such a manner that said model bit line load transistor is non-conductive responsive to said input clock signal being active and conductive responsive to said input clock signal being inactive; a third transistor, having a source-drain path connected between the intermediate node and the output of the bias circuit, and having a gate biased so that said third transistor is conductive while the model bit line load transistor is conductive, said third transistor having a size corresponding to one of the pass transistors; and a discharge transistor, having a source-drain path coupled between the output of said bias circuit and a reference voltage, and having a gate coupled to receive the input clock signal in such a manner that said discharge transistor is non-conductive responsive to said input clock signal being inactive and conductive responsive to said input clock signal being active.

Claim 13

In an integrated circuit memory of the type having a plurality of memory cells, each comprising cross-coupled inverters connectable to differential bit lines by way of pass transistors controlled by a word line signal, each of the cross-coupled inverters comprising a drive transistor and a load, a delay circuit for generating an output clock signal responsive to an input clock signal, delayed in a manner corresponding to the response of the memory cell when accessed, comprising: a first transistor, having a size corresponding to one of the pass transistors, having a gate for receiving the input clock signal, and having a source-drain path coupled on one side to an output node; a second transistor, having a size corresponding to one of the drive transistors, having a gate, and having a source-drain path coupled between a second side of the source-drain path of the first transistor and a reference voltage; and a bias circuit, having an output coupled to the gate of the second transistor, for generating a voltage corresponding to a high level voltage in the memory cell, comprising: a model bit line load transistor, having a source-drain path coupled between a power supply voltage and an intermediate node, and having a gate coupled to receive the input clock signal in such a manner that said model bit line load transistor is non-conductive responsive to said input clock signal being active and conductive responsive to said input clock signal being inactive; a third transistor, having a source-drain path connected between the intermediate node and the output of the bias circuit, and having a gate biased so that said third transistor is conductive while the model bit line load transistor is conductive, said third transistor having a size corresponding to one of the pass transistors; and a discharge transistor, having a source-drain path coupled between the output of said bias circuit and a reference voltage, and having a gate coupled to receive the input clock signal in such a manner that said discharge transistor is non-conductive responsive to said input clock signal being inactive and conductive responsive to said input clock signal being active.

Claim 14

The delay circuit of claim 11, wherein the gate of the third transistor is biased to a power supply voltage.

Claim 15

An integrated circuit memory, comprising: a plurality of memory cells arranged in rows and columns, each column associated with a pair of differential bit lines, and each row associated with a word line, each of said memory cells comprising: a pair of cross-coupled inverters, each including a drive transistor and a load; a pair of pass transistors, each having a source-drain path connected between one of the cross-coupled inverters and one of the differential bit lines, and each having a gate controlled by a word line; a clocked sense amplifier, coupled to one of the pairs of differential bit lines, and having a clock input; a delay circuit having an output to the clock input of the clocked sense amplifier, for generating a sense amplifier clock signal responsive to an input clock signal, comprising: a first transistor, having a size corresponding to one of the pass transistors, having a gate for receiving the input clock signal, and having a source-drain path coupled on one side to an output node; a second transistor, having a size corresponding to one of the drive transistors, having a gate, and having a source-drain path coupled between a second side of the source-drain path of the first transistor and a reference voltage; and a bias circuit, having an output coupled to the gate of the second transistor, for generating a voltage at its output corresponding to a high level voltage in one of the plurality of memory cells.

Claim 16

An integrated circuit memory, comprising: a plurality of memory cells arranged in rows and columns, each column associated with a pair of differential bit lines, and each row associated with a word line, each of said memory cells comprising: a pair of cross-coupled inverters, each including a drive transistor and a load; a pair of pass transistors, each having a source-drain path connected between one of the cross-coupled inverters and one of the differential bit lines, and each having a gate controlled by a word line; a clocked sense amplifier, coupled to one of the pairs of differential bit lines, and having a clock input; a delay circuit having an output to the clock input of the clocked sense amplifier, for generating a sense amplifier clock signal responsive to an input clock signal, comprising: a first transistor, having a size corresponding to one of the pass transistors, having a gate for receiving the input clock signal, and having a source-drain path coupled on one side to an output node; a second transistor, having a size corresponding to one of the drive transistors, having a gate, and having a source-drain path coupled between a second side of the source-drain path of the first transistor and a reference voltage; and a bias circuit, having an output coupled to the gate of the second transistor, for generating a voltage at its output corresponding to a high level voltage in one of the plurality of memory cells.

Claim 17

The memory of claim 13, wherein the delay circuit further comprises: a capacitive load coupled to the output node, having a capacitance modeling a load of one of the bit lines.

Claim 18

The memory of claim 13, wherein the delay circuit further comprises: a pull-up transistor, having a source-drain path coupled between the output node of the delay circuit and a power supply voltage, and having a gate coupled to receive the input clock signal, for biasing the output node toward the power supply voltage responsive to the input clock signal being in an inactive state.

Claim 19

The memory of claim 13, further comprising: a plurality of bit line loads, each coupled between one of the bit lines and a reference voltage; and wherein said bias circuit comprises: a model bit line load, having characteristics corresponding to one of the bit line loads, and coupled on one side to a power supply voltage; and a third transistor, having a source-drain path coupled between said model bit line load and the output of the bias circuit, and having a gate biased to a voltage such that said third transistor is conductive, said third transistor having a size corresponding to one of the pass transistors; and a low load, coupled between the output of the bias circuit and a reference voltage.

Claim 20

The memory of claim 16, wherein said model bit line load comprises a p-channel transistor.

Claim 21

The memory of claim 16, wherein the delay circuit further comprises: an isolate transistor, having a source-drain path coupled in series with said model bit line load between the output of said bias circuit and the power supply voltage, and having a gate for receiving a select signal which, when inactive, makes said isolate transistor non-conductive; and a discharge transistor, having a source-drain path coupled between the output of said bias circuit and a reference voltage, and having a gate for receiving the select signal which, when inactive, makes said discharge transistor conductive.

Claim 22

The memory of claim 13, further comprising: a plurality of bit line loads, each coupled between one of the bit lines and a reference voltage; and wherein said bias circuit comprises: a model bit line load transistor, having characteristics corresponding to one of the bit line loads, having a source-drain path coupled between a power supply voltage and an intermediate node, and having a gate coupled to receive the input clock signal in such a manner that said model bit line load transistor is non-conductive responsive to said input clock signal being active and conductive responsive to said input clock signal being inactive; a third transistor, having a source-drain path connected between the intermediate node and the output of the bias circuit, and having a gate biased so that said third transistor is conductive while the model bit line load transistor is conductive, said third transistor having a size corresponding to one of the pass transistors; and a discharge transistor, having a source-drain path coupled between the output of said bias circuit and a reference voltage, and having a gate coupled to receive the input clock signal in such a manner that said discharge transistor is non-conductive responsive to said input clock signal being inactive and conductive responsive to said input clock signal being active.

Claim 23

The memory of claim 13, wherein the memory cell high level voltage corresponds to a power supply voltage less the threshold voltage of one of the pair of pass transistors.