Semiconductor memory circuit having a delay circuit

Claim 2

A semiconductor memory circuit comprising: a memory cell array including a plurality of memory cells; address decoding means for decoding an address signal supplied from an external circuit, a decoded address signal being supplied to the memory cell array; data writing means for writing write data supplied from the external circuit into the memory cell array; data read-out means for reading out data stored in the memory cell array; and variable delay means for delaying the write data supplied from the external circuit by a delay time which is variably determined depending on a potential level of a write enable signal which is supplied from the external circuit and enables the data write means to store a delayed write data supplied from the variable delay means into the memory cell array.

Claim 3

A semiconductor memory circuit as claimed in claim 1, wherein the variable delay means comprises Schmitt trigger means having two threshold levels with respect to the write data supplied from the external circuit.

Claim 4

A semiconductor memory circuit as claimed in claim 1, wherein the variable delay means comprises two Schmitt trigger inverter means which are connected in series and two control means provided for the respective Schmitt trigger inverter means for determining the delay time provided by the respective Schmitt trigger inverter means in response to the level of the write enable signal.

Claim 5

A semiconductor memory circuit as claimed in claim 3, wherein each of the Schmitt trigger inverter means comprises first and second complementary metal oxide semiconductor (CMOS) inverters.

Claim 6

A semiconductor memory circuit as claimed in claim 4, wherein the first inverter of each of the Schmitt trigger inverter means comprises first P-channel and N-channel transistors and the second inverter comprises second P-channel and N-channel transistors, and wherein drains of first and second P-channel transistors are connected to a positive power source, and a source of the second N-channel transistor is connected to a negative power source, and wherein drains of second P-channel and N-channel transistors and a source of the first N-channel transistor are connected to one another and also to the corresponding control means, and wherein gates of all the transistors are mutually connected to function as an input of each of the two Schmitt trigger inverter means, and wherein drains of the first P-channel and N-channel transistors are mutually connected to function as an output of each of the two Schmitt trigger inverter means.

Claim 7

A semiconductor memory circuit as claimed in claim 5, wherein each of the control means comprises an N-channel metal oxide semiconductor transistor, a drain of which is connected to the drain of the second P-channel transistor, and a source of which is connected to the negative power source, and wherein the write enable signal is supplied to gates of the N-channel MOS transistor of the control means through an inverter.

Claim 8

A semiconductor memory circuit as claimed in claim 1, wherein the variable delay means comprises two inverter circuits, and wherein each of the inverter circuits comprises a complementary metal oxide semiconductor (CMOS) inverter comprising a first P-channel transistor and a first N-channel transistor, and wherein gates of the first P-channel and N-channel transistors are connected to each other to function as an input to which the write data signal is applied, and drains thereof are connected to each other to function as an output through which an inverted signal of the write data signal is outputted, and wherein a source of the first P-channel transistor is connected to a positive power source through second and third P-channel transistors, and a source of the first N-channel transistor is connected to an negative power source through second and third N-channel transistors, and wherein gates of the second P-channel and N-channel transistors are connected to the negative and positive power source, respectively, and gates of the third N-channel and P-channel transistors are supplied to the write enable signal and an inverted signal thereof.

Claim 9

A semiconductor memory circuit as claimed in claim 1, wherein the variable delay means adds a relatively small delay time to the write data when the write enable signal is active, and wherein the variable delay means adds a relatively large delay time to the write data when the write enable signal is inactive.

Claim 10

A semiconductor memory circuit comprising: a memory cell array including a plurality of memory cells; data writing means for writing write data supplied from an external circuit into the memory cell array; data read-out means for reading out data stored in the memory cell array; address buffer means for delaying an address signal supplied from the external circuit by a delay time which is variably determined depending on potential levels of row address and column address strobe signals which are supplied from the external circuit; and address decoding means for decoding a delayed address signal derived from the address buffer means, a decoded address being supplied to the memory cell array.

Claim 11

A semiconductor memory circuit comprising: a memory cell array including a plurality of memory cells; data writing means for writing write data supplied from an external circuit into the memory cell array; data read-out means for reading out data stored in the memory cell array; address buffer means for delaying an address signal supplied from the external circuit by a delay time which is variably determined depending on potential levels of row address and column address strobe signals which are supplied from the external circuit; and address decoding means for decoding a delayed address signal derived from the address buffer means, a decoded address being supplied to the memory cell array.

Claim 12

A semiconductor memory circuit as claimed in claim 9, wherein the address buffer means comprises two variable delay means each provided with respect to the respective row and column address strobe signals, and each of the variable delay means comprises a Schmitt trigger means having two threshold levels with respect to the address signal supplied from the external circuit.

Claim 13

A semiconductor memory circuit as claimed in claim 10, wherein each of the two variable delay means comprises two Schmitt trigger inverter means which are connected in series and two control means provided for the respective Schmitt trigger inverter means for determining the delay time determined by the respective Schmitt trigger inverter means in response to the levels of the row and column address strobe signals.

Claim 14

A semiconductor memory circuit as claimed in claim 11, wherein each of the Schmitt trigger inverter means comprises first and second complementary metal oxide semiconductor (CMOS) inverters.

Claim 15

A semiconductor memory circuit as claimed in claim 12, wherein the first inverter of each of the Schmitt trigger inverter means comprises first P-channel and N-channel transistors and the second inverter comprises second P-channel and N-channel transistors, and wherein drains of first and second P-channel transistors are connected to a positive power source, and a source of the second N-channel transistor is connected to a negative power source, and wherein drains of second P-channel and N-channel transistors and a source of the first N-channel transistor are connected to one another and also to the corresponding control means, and wherein gates of all the transistors are mutually connected to function as an input of each of the two Schmitt trigger inverter means, and wherein drains of the first P-channel and N-channel transistors are mutually connected to function as an output of each of the two Schmitt trigger inverter means.

Claim 16

A semiconductor memory circuit as claimed in claim 13, wherein each of the control means comprises an N-channel metal oxide semiconductor transistor, a drain of which is connected to the drain of the second P-channel transistor, and a source of which is connected to the negative power source, and wherein the corresponding address strobe signal is supplied to gates of the N-channel MOS transistor of the control means.

Claim 17

A semiconductor memory circuit as claimed in claim 9, wherein the variable delay means comprises two inverter circuits, and wherein each of the inverter circuits comprises a complementary metal oxide semiconductor (CMOS) inverter comprising a first P-channel transistor and a first N-channel transistor, and wherein gates of the first P-channel and N-channel transistors are connected to each other to function as an input to which the corresponding address strobe signal is applied, and drains thereof are connected to each other to function as an output through which an inverted signal of the address signal is outputted, and wherein a source of the first P-channel transistor is connected to a positive power source through second and third P-channel transistors, and a source of the first N-channel transistor is connected to an negative power source through second and third N-channel transistors, and wherein gates of the second P-channel and N-channel transistors are connected to the negative and positive power source, respectively, and gates of the third N-channel and P-channel transistors are supplied to the corresponding address strobe signal and an inverted signal thereof.

Claim 18

A semiconductor memory circuit as claimed in claim 9, wherein the address buffer means adds a relatively small delay time to the address signal when the row address and column address strobe signals are active, and wherein the address buffer means adds a relatively large delay time to the address signal when the row address and column address strobe signals are inactive.