US4740923A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory circuit and method of controlling the same
Assignee: Hitachi Microcomputer System Ltd
•
Filing: 1985-11-19
•
Granted: 1988-04-26
•
Expires: 2005-11-19
Abstract
Abstract A memory circuit is divided into a plurality of memory blocks, and an address register and a delay register are disposed in each memory block. Therefore, a read or write operation and a shifting operation of the address for storing data inside a memory matrix can be realized by a pipeline technique, and hence a memory circuit having a high processing speed is obtained.
Inventors
- 👤 Kenji Kaneko
- 👤 Jun Ishida
- 👤 Yoshimune Hagiwara
- 👤 Hitoshi Matsushima
- 👤 Hirotada Ueda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:28
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07314; G01R1/07328; G01R1/06711; G01R1/06716; G01R1/06722; G01R1/07364; G01R1/07378; H; H05; H05K; H05K13/00; H05K13/08; H05K13/082
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
139 words
A memory circuit consisting of n memory blocks, each of said memory blocks comprising: a memory matrix; address means for accessing data inside said memory matrix; data input means for inputting data into said memory matrix; data output means for outputting data from said memory matrix; address registers coupled with said address means for storing a data address; and at least one delay register coupled with said data output means for storing data that is read out of said memory matrix, said at least one delay register of each of said memory blocks being coupled with a data input means of at least one other memory block, such that data held by said at least one delay register is input into said data input means of said at least one other memory block in accordance with a predetermined instruction.
Claim 2
Dependent Claim
139 words
A memory circuit consisting of n memory blocks, each of said memory blocks comprising: a memory matrix; address means for accessing data inside said memory matrix; data input means for inputting data into said memory matrix; data output means for outputting data from said memory matrix; address registers coupled with said address means for storing a data address; and at least one delay register coupled with said data output means for storing data that is read out of said memory matrix, said at least one delay register of each of said memory blocks being coupled with a data input means of at least one other memory block, such that data held by said at least one delay register is input into said data input means of said at least one other memory block in accordance with a predetermined instruction.
Claim 3
Dependent Claim
67 words
The memory circuit as defined in claim 1, further comprising means for writing the data which has been input into the data input means of a first memory block from the delay register of a second memory block in accordance with said predetermined instruction, into the memory matrix of said first memory block based on a data address stored in the address register of said memory block.
Claim 4
Dependent Claim
43 words
The memory circuit as defined in claim 1, wherein said address registers include means coupled with an address bus for accepting an address from said address bus when an address of the memory block in which said address register is disposed is designated.
Claim 5
Dependent Claim
37 words
The memory circuit as defined in claim 3, further comprising read-write means for either reading data from said memory matrix or writing data into said memory matrix on the basis of the address from said data bus.
Claim 6
Dependent Claim
175 words
A memory circuit comprising: at least first and second memory blocks each having a plurality of address locations; at least first and second data store means electrically connected to said at least first and second memory blocks, respectively; address means for accessing said first memory block to provide first data therefrom to said first data store means in response to a first address signal from said address bus and for accessing said second memory block to provide second data therefrom to said second data store means in response to a second address signal from said address bus, said address means and said at least first and second data store means being responsive to a control signal so as to transfer said first data stored in said first data store means to said second memory block in response to a third address signal from said address bus and for transferring said second data stored in said second data store means to said first memory block in response to a fourth address signal from said address bus.
Claim 7
Dependent Claim
175 words
A memory circuit comprising: at least first and second memory blocks each having a plurality of address locations; at least first and second data store means electrically connected to said at least first and second memory blocks, respectively; address means for accessing said first memory block to provide first data therefrom to said first data store means in response to a first address signal from said address bus and for accessing said second memory block to provide second data therefrom to said second data store means in response to a second address signal from said address bus, said address means and said at least first and second data store means being responsive to a control signal so as to transfer said first data stored in said first data store means to said second memory block in response to a third address signal from said address bus and for transferring said second data stored in said second data store means to said first memory block in response to a fourth address signal from said address bus.
Claim 8
Dependent Claim
33 words
The memory circuit as defined in claim 5, wherein each of said at least first and second data store means comprises a single register for temporarily storing said first and second data, respectively.
Claim 9
Dependent Claim
53 words
The memory circuit as defined in claim 5, wherein each of said at least first and second data store means comprises a plurality of shift registers for storing first and second data, respectively, and for sequentially shifting said first and second data, respectively, through at least one of said plurality of shift registers.
Claim 10
Independent Claim
138 words
A method of controlling a memory circuit which includes n memory blocks (n being an integer ≧2), n data store means and an address means for accessing said n memory blocks comprising the steps of: accessing a first memory block to provide first data therefrom to a first data store means in response to a first address signal; accessing a second memory block to provide second data therefrom to a second data store means in response to a second address signal; transferring said first data stored in said first data store means to said second memory block in response to a predetermined command signal and a third address signal; and transferring said second data stored in said second data store means to said first memory block in response to said predetermined command signal and a fourth address signal.
Claim 11
Independent Claim
138 words
A method of controlling a memory circuit which includes n memory blocks (n being an integer ≧2), n data store means and an address means for accessing said n memory blocks comprising the steps of: accessing a first memory block to provide first data therefrom to a first data store means in response to a first address signal; accessing a second memory block to provide second data therefrom to a second data store means in response to a second address signal; transferring said first data stored in said first data store means to said second memory block in response to a predetermined command signal and a third address signal; and transferring said second data stored in said second data store means to said first memory block in response to said predetermined command signal and a fourth address signal.
Claim 12
Independent Claim
120 words
A method of controlling a memory circuit which includes n memory blocks (n being an integer ≧2) with an address register and a delay register in each of said n memory blocks, said method comprising the steps of: storing an address in the address register of a predetermined memory block only when said address corresponds to said predetermined memory block; reading out data from said address in said predetermined memory block; storing data in said delay register corresponding to said predetermined memory block; and writing previously stored data from said delay register into an address of a different memory block at substantially the same time that said data is stored in said delay register in response to a read-modify-write instruction.
Claim 13
Independent Claim
120 words
A method of controlling a memory circuit which includes n memory blocks (n being an integer ≧2) with an address register and a delay register in each of said n memory blocks, said method comprising the steps of: storing an address in the address register of a predetermined memory block only when said address corresponds to said predetermined memory block; reading out data from said address in said predetermined memory block; storing data in said delay register corresponding to said predetermined memory block; and writing previously stored data from said delay register into an address of a different memory block at substantially the same time that said data is stored in said delay register in response to a read-modify-write instruction.
References Cited (Backward Citations)
US4608671A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-04-26 | 1991-10-26 | 1992-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-04-26 | 1995-10-26 | 1996-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-04-26 | 1999-10-26 | 2000-04-26 | $7700.00 | Window Closed / Lapsed |