US5776806A
Expired / Lapsed
US
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Method of forming CMOS integrated circuitry having halo regions
Assignee: Round Rock Research LLC
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Filing: 1997-05-30
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Granted: 1998-07-07
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Expires: 2017-05-30
Abstract
Abstract A method of forming CMOS integrated circuitry includes, a) providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to an area of the substrate for formation of an NMOS transistor, a second gate line being positioned relative to an area of the substrate for formation of a PMOS transistor; b) masking the second gate line and the PMOS substrate area while conducting a p-type halo ion implant into the NMOS substrate area adjacent the first gate line, the p-type halo ion implant being conducted at a first energy level to provide a p-type first impurity concentration at a first depth within the NMOS substrate area; and c) in a common step, blanket ion implanting phosphorus into both the NMOS substrate area and the PMOS substrate area adjacent the first and the second gate lines to form both NMOS LDD regions and PMOS n-type halo regions, respectively, the phosphorus implant being conducted at a second energy level to provide an n-type second impurity concentration at a second depth within both the PMOS substrate area and the NMOS substrate area, the first energy level and the first depth being greater than the second energy level and the second depth, respectively. Methods of forming memory and other CMOS integrated circuitry are also disclosed involving optimization of different NMOS transistors.
Inventors
- 👤 Charles H. Dennison
- 👤 Mark Helm
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:06
CPC Classifications
H; H10; H10B; H10B12/00; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0167; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/856; H10D84/8311; H10D84/8312
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
83 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions and at least one of the PMOS regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, and the PMOS source/drain regions.
Claim 2
Independent Claim
83 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions and at least one of the PMOS regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, and the PMOS source/drain regions.
Claim 3
Independent Claim
100 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; forming memory array transistor source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions, at least one of the PMOS regions, and the memory array source/drain regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, the PMOS source/drain regions, and the memory array transistor source/drain regions.
Claim 4
Independent Claim
100 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; forming memory array transistor source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions, at least one of the PMOS regions, and the memory array source/drain regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, the PMOS source/drain regions, and the memory array transistor source/drain regions.
Claim 5
Independent Claim
83 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions and at least one of the PMOS regions; and no more than three masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, and the PMOS source/drain regions.
Claim 6
Independent Claim
83 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions and at least one of the PMOS regions; and no more than three masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, and the PMOS source/drain regions.
Claim 7
Independent Claim
100 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; forming memory array transistor source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions, at least one of the PMOS regions, and the memory array source/drain regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, the PMOS source/drain regions, and the memory array transistor source/drain regions.
Claim 8
Independent Claim
100 words
A method of forming CMOS circuitry comprising: forming NMOS halo regions, NMOS LDD regions and NMOS source/drain regions; forming PMOS halo regions and PMOS source/drain regions; forming memory array transistor source/drain regions; at least one maskless blanket doping step to form at least one of the NMOS regions, at least one of the PMOS regions, and the memory array source/drain regions; and no more than two masking layer provision steps to collectively form the NMOS halo regions, the NMOS LDD regions, the NMOS source/drain regions, the PMOS halo regions, the PMOS source/drain regions, and the memory array transistor source/drain regions.
Claim 9
Independent Claim
149 words
A method of forming CMOS integrated circuitry on a substrate, comprising the steps of: providing said substrate having first and second portions; providing first and second gate areas on said substrate, the first gate area being positioned relative to the first portion of said substrate for formation of a first transistor, the second gate area being positioned relative to the second portion of said substrate for formation of a second transistor; forming a first transistor gate over the first gate area and a second transistor gate over the second gate area; masking said second transistor gate and said second portion of the substrate and conducting an implant of a second conductivity-type impurity into said first portion; removing said masking; after removing the masking, forming sidewall spacers adjacent the transistor gates; and after forming the sidewalls adjacent the transistor gates, implanting an impurity into said first and second substrate portions.
Claim 10
Independent Claim
149 words
A method of forming CMOS integrated circuitry on a substrate, comprising the steps of: providing said substrate having first and second portions; providing first and second gate areas on said substrate, the first gate area being positioned relative to the first portion of said substrate for formation of a first transistor, the second gate area being positioned relative to the second portion of said substrate for formation of a second transistor; forming a first transistor gate over the first gate area and a second transistor gate over the second gate area; masking said second transistor gate and said second portion of the substrate and conducting an implant of a second conductivity-type impurity into said first portion; removing said masking; after removing the masking, forming sidewall spacers adjacent the transistor gates; and after forming the sidewalls adjacent the transistor gates, implanting an impurity into said first and second substrate portions.
References Cited (Backward Citations)
US4342149A
Cited
US5141890A
Cited
US4474624A
Cited
US4530150A
Cited
JPS62160754A
Cited
US4950617A
Cited
US4745083A
Cited
US4764477A
Cited
US4933994A
Cited
US5024960A
Cited
US4753898A
Cited
US4771014A
Cited
US4968639A
Cited
US4997782A
Cited
US5015595A
Cited
US4876213A
Cited
US5036019A
Cited
US5170232A
Cited
US5365110A
Cited
US5286665A
Cited
US5106768A
Cited
US5217910A
Cited
US5166087A
Cited
US5422506A
Cited
US5385857A
Cited
US5532176A
Cited
US5340756A
Cited
US5449937A
Cited
US5395787A
Cited
US5413945A
Cited
US5405791A
Cited
US5534449A
Cited
US5683927A
Cited
US5670397A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-07-06 | 2002-01-05 | 2002-07-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-07-06 | 2006-01-05 | 2006-07-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-07-06 | 2010-01-05 | 2010-07-07 | $7700.00 | Window Closed / Lapsed |