US5532176A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for fabricating a complementary MIS transistor
Assignee: Denso Corp
•
Filing: 1994-07-26
•
Granted: 1996-07-02
•
Expires: 2014-07-26
Abstract
Abstract A CMIS transistor suitable for device miniaturization, elimination of degradation of operational characteristics by hot carrier effect, and elimination of decrease of threshold voltage caused by short channel effect, includes a laterally spreading N-type diffusion region having an impurity concentration level higher than P-type and N-type wells but lower than source and drain regions, such that the N-type diffusion region extends laterally into a part located immediately below an edge of an insulating gate and has a depth smaller than a depth of the source and drain regions. The device is thereby capable of increasing the width of depletion layer at the bottom of the source and drain regions while maintaining effectiveness as a punch-thorough stopper. Thereby, the junction capacitance at the source and drain regions is reduced and the operational speed of the device improved in the P-channel transistor part in the device. In the N-channel transistor part, an effective suppression of punch-through is achieved because of the small diffusion depth of the N-type diffusion region. Thereby, the decrease of threshold voltage caused by the short channel effect is effectively eliminated even when the gate length of the transistor is reduced.
Inventors
- 👤 Mitsutaka Katada
- 👤 Hidetoshi Muramoto
- 👤 Seizi Fuzino
- 👤 Tadashi Hattori
- 👤 Katsunori Abe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 03:12
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
454 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion regions have an impurity concentration level that is higher than an impurity concentration level in said P-type well and said N-type well, and such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well from a first edge and a second edge of said insulating gate, said step of forming said N-type diffusion regions being conducted, in each of said P-type well and said N-type well, by applying an ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well, and such that said N-type source region and said N-type drain region have a depth at least equal to a depth of said N-type diffusion region in said P-type well, said step of forming said N-type source region and said N-type drain region being conducted in self-alignment to said insulating gate provided on said P-type well, such that said N-type source region and said N-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said N-type well, and such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well, said step of forming said P-type source region and said P-type drain region being conducted in self-alignment to said insulating gate provided on said N-type well, such that said P-type source region and said P-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said N-type well.
Claim 2
Independent Claim
454 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion regions have an impurity concentration level that is higher than an impurity concentration level in said P-type well and said N-type well, and such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well from a first edge and a second edge of said insulating gate, said step of forming said N-type diffusion regions being conducted, in each of said P-type well and said N-type well, by applying an ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well, and such that said N-type source region and said N-type drain region have a depth at least equal to a depth of said N-type diffusion region in said P-type well, said step of forming said N-type source region and said N-type drain region being conducted in self-alignment to said insulating gate provided on said P-type well, such that said N-type source region and said N-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said N-type well, and such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well, said step of forming said P-type source region and said P-type drain region being conducted in self-alignment to said insulating gate provided on said N-type well, such that said P-type source region and said P-type drain region have respective junctions defining a lateral boundary thereof, respectively in alignment to said first and second edges of said insulating gate on said N-type well.
Claim 3
Dependent Claim
48 words
A method as claimed in claim 1, wherein said step of forming said insulating gate comprises a step for forming said insulating gate to have oblique side walls such that a lateral width of said insulating gate decreases as increasing distance from a principal surface of said substrate.
Claim 4
Dependent Claim
181 words
A method as claimed in claim 1, wherein said method further comprises, after said step of forming said N-type diffusion region but before said step of forming said P-type source and drain regions, a step of forming a P-type diffusion region within said N-type well in correspondence to a part located immediately below said insulating gate formed on said N-type well, such that said P-type diffusion region has an impurity concentration level higher than the impurity concentration level of said N-type diffusion region, such that said P-type diffusion region extends into a region located immediately below said insulating gate of said N-type well, and such that said P-type diffusion region has a lateral extension and a depth that are smaller than a lateral extension and a depth of said N-type diffusion region, said step of forming said P-type diffusion region comprising a step of injecting P-type dopant ions into said substrate obliquely with an angle of at least 10 degrees with respect to said principal surface of said substrate, while using said insulating gate on said N-type well as a mask.
Claim 5
Dependent Claim
39 words
A method as claimed in claim 3, wherein said P-type diffusion region is formed such that said impurity concentration level of said P-type diffusion region is smaller than said impurity concentration level of said P-type source and drain regions.
Claim 6
Dependent Claim
34 words
A method as claimed in claim 1, wherein said step of forming said N-type diffusion region by introducing said N-type dopant ions comprises a step of introducing phosphorus ions as said N-type dopant ions.
Claim 7
Dependent Claim
30 words
A method as claimed in claim 5, wherein said step of forming said N-type source and drain regions comprises a step of introducing phosphorus ions and arsenic ions as dopant.
Claim 8
Dependent Claim
17 words
A method as claimed in claim 1, wherein said oblique angle ranges from 10° to 75° C.
Claim 9
Independent Claim
288 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well, wherein said step of forming said N-type diffusion regions includes a first ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well, and such that said N-type source region and said N-type drain region have a depth at least equal to a depth of said N-type diffusion region in said P-type well while keeping a lateral diffusion length thereof smaller than said N-type diffusion region in said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well while said P-type source region and said P-type drain region are aligned with edges of said insulating gate provided on said N-type well, respectively.
Claim 10
Independent Claim
288 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well, wherein said step of forming said N-type diffusion regions includes a first ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well, and such that said N-type source region and said N-type drain region have a depth at least equal to a depth of said N-type diffusion region in said P-type well while keeping a lateral diffusion length thereof smaller than said N-type diffusion region in said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well while said P-type source region and said P-type drain region are aligned with edges of said insulating gate provided on said N-type well, respectively.
Claim 11
Dependent Claim
49 words
A method as claimed in claim 8, wherein said step of forming said insulating gate comprises a step for forming said insulating gate to have oblique side walls such that a lateral width of said insulating gate decreases with increasing distance away from a principal surface of said substrate.
Claim 12
Dependent Claim
131 words
A method as claimed in claim 8, further comprising, after said step of forming said N-type diffusion region but before said step of forming said P-type source and drain regions, a step of forming a P-type diffusion region within said N-type well in correspondence to a part located immediately below said insulating gate formed on said N-type well, such that said P-type diffusion region has an impurity concentration level lower than the impurity concentration level of said P-type source and drain regions, such that said P-type diffusion region extends into a region located immediately below said insulating gate of said N-type well, and such that said P-type diffusion region has a lateral extension and a depth that are smaller than a lateral extension and a depth of said N-type diffusion region.
Claim 13
Dependent Claim
57 words
A method as claimed in claim 10, wherein said step of forming said P-type diffusion region includes a step of implanting P-type dopant ions into said substrate obliquely with an angle of at least 10 degrees with respect to said principal surface of said substrate, while using said insulating gate on said N-type well as a mask.
Claim 14
Dependent Claim
28 words
A method as claimed in claim 8, wherein said step of forming said N-type diffusion region includes a step of introducing phosphorus ions as said N-type dopant ions.
Claim 15
Dependent Claim
30 words
A method as claimed in claim 12, wherein said step of forming said N-type source and drain regions includes a step of introducing phosphorus ions and arsenic ions as dopant.
Claim 16
Dependent Claim
86 words
A method as claimed in claim 8, further comprising a step of introducing supplemental N-type dopant ions in said P-type well after said step of forming said N-type diffusion region, wherein said step of introducing supplemental N-type dopant ions includes a second ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted with an angle of at least 10 degrees with respect to a principal surface of said substrate while using said insulating gate on said P-type well as a mask.
Claim 17
Dependent Claim
32 words
A method as claimed in claim 14, wherein said step of forming said P-type source and drain regions is performed prior to said step of forming said N-type source and drain regions.
Claim 18
Dependent Claim
17 words
A method as claimed in claim 8, wherein said oblique angle ranges from 10° to 75° C.
Claim 19
Independent Claim
240 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well, wherein said step of forming said N-type diffusion regions includes an ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well while said P-type source region and said P-type drain region are aligned with edges of said insulating gate provided on said N-type well, respectively.
Claim 20
Independent Claim
240 words
A method for fabricating a complementary MIS transistor, comprising the steps of: defining a P-type well and an N-type well in a substrate; providing an insulating gate on each of said P-type well and said N-type well; forming an N-type diffusion region in each of said P-type well and said N-type well simultaneously, such that said N-type diffusion region extends laterally into a region located immediately below said insulating gate in each of said P-type well and said N-type well, wherein said step of forming said N-type diffusion regions includes an ion implantation process of N-type dopant ions such that said N-type dopant ions are implanted at an oblique angle with respect to a principal surface of said substrate while using said insulating gate as a mask; forming an N-type source region and an N-type drain region in said P-type well, such that said N-type source region and said N-type drain region have an impurity concentration level larger than the impurity concentration level of said N-type diffusion region in said P-type well; and forming a P-type source region and a P-type drain region in said N-type well, such that said P-type source region and said P-type drain region have a depth at least equal to a depth of said N-type diffusion region in said N-type well while said P-type source region and said P-type drain region are aligned with edges of said insulating gate provided on said N-type well, respectively.
Claim 21
Dependent Claim
17 words
A method as claimed in claim 17, wherein said oblique angle ranges from 10° to 75° C.
References Cited (Backward Citations)
US5247199A
Cited
US4924277A
Cited
JPH01212471A
Cited
JPH01212470A
Cited
US5061975A
Cited
US5122474A
Cited
JPH0212960A
Cited
US5247198A
Cited
US5170232A
Cited
JPH03138951A
Cited
JPH04211178A
Cited
JPH03262130A
Cited
US5216272A
Cited
US5100820A
Cited
US5166087A
Cited
JPH05102180A
Cited
JPH05299594A
Cited
US5413945A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |