US5340756A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for producing self-aligned LDD CMOS, DMOS with deeper source/drain and P-base regions and, bipolar devices on a common substrate
Assignee: Fuji Electric Co Ltd
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Filing: 1993-06-02
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Granted: 1994-08-23
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Expires: 2013-06-02
Abstract
Abstract A low-concentration region is formed by ion implanting a P-well with P + using a gate as a mask, then an N-well is ion-implanted with As + and B + using a resist film and the gate as a mask to form a DMOSFET having a double-diffused drain structure. Then, the gate and an insulation material are used as a mask to ion-implant the P-well with As + to form a CMOSFET having a lightly doped drain structure. After that, the N-well is ion-implanted with BF 2 + through an opening to connect a P base region with a P base-contact region. The source/drain and p-base regions of the DMOS device are formed deeper than those of the CMOS device. Incorporation of a bipolar transistor is also disclosed. All devices are formed on the same substrate.
Inventors
- 👤 Yoshihiko Nagayasu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 03:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/0123; H10D84/0126; H10D84/0147; H10D84/0165; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
139 words
A method for producing a semiconductor device having a CMOSFET and an N-channel double-diffused MOSFET in a semiconductor substrate, comprising the steps of: forming source-drain regions by implanting a first dopant using a gate of an N-channel MOSFET constructing said CMOSFET as a mask; forming source-drain regions and a p base region of said N-channel double-diffused MOSFET deeper than said source-drain regions by successively implanting a second dopant and a third dopant using gates of said N-channel double-diffused MOSFET as a mask; forming oxide films on side walls of individual gates of the N-channel MOSFET, a P-channel MOSFET constructing said CMOSFET, and said N-channel double-diffused MOSFET; and forming an LDD structure by implanting into the source-drain regions of said N-channel MOSFET with a fourth dopant using the gate of said N-channel MOSFET and said oxide films as a mask.
Claim 2
Independent Claim
139 words
A method for producing a semiconductor device having a CMOSFET and an N-channel double-diffused MOSFET in a semiconductor substrate, comprising the steps of: forming source-drain regions by implanting a first dopant using a gate of an N-channel MOSFET constructing said CMOSFET as a mask; forming source-drain regions and a p base region of said N-channel double-diffused MOSFET deeper than said source-drain regions by successively implanting a second dopant and a third dopant using gates of said N-channel double-diffused MOSFET as a mask; forming oxide films on side walls of individual gates of the N-channel MOSFET, a P-channel MOSFET constructing said CMOSFET, and said N-channel double-diffused MOSFET; and forming an LDD structure by implanting into the source-drain regions of said N-channel MOSFET with a fourth dopant using the gate of said N-channel MOSFET and said oxide films as a mask.
Claim 3
Dependent Claim
51 words
A method as claimed in claim 1, further comprising the step of introducing a fifth dopant to form source-drain regions of said P-channel MOSFET of said CMOSFET and at the same time to form a P base contact region partly overlapping with said P base region of said N-channel double-diffused MOSFET.
Claim 4
Dependent Claim
84 words
A method as claimed in claim 1, wherein said device further comprising an NPN transistor formed in said semiconductor substrate and the method further comprising the steps of forming source-drain regions of said NPN transistor by selectively introducing said second dopant simultaneously with the formation of the source-drain regions of said N-channel double-diffused MOSFET and forming a p base region of said NPN transistor by selectively introducing said third dopant simultaneously with the formation of the P base region of said N-channel double-diffused MOSFET.
Claim 5
Dependent Claim
50 words
A method as claimed in claim 3, further comprising the step of introducing a fifth dopant to form source-drain regions of a P-channel MOSFET of said CMOSFET and at the same time to form a P base outer region partly overlapping with the P base region of said NPN transistor.
Claim 6
Dependent Claim
51 words
A method as claimed in claim 3, further comprising the step of introducing a fifth dopant to form source-drain regions of said P-channel MOSFET of said CMOSFET and at the same time to form a P base contact region partly overlapping with said P base region of said N-channel double-diffused MOSFET.
Claim 7
Independent Claim
177 words
A method for producing a semiconductor device having a CMOSFET and a P-channel double-diffused MOSFET in a same semiconductor substrate, comprising the steps of: forming an N - regions for preparing an LDD structure in an N-channel MOSFET constructing said CMOSFET and N base regions of said P-channel double-diffused MOSFET by implanting a first dopant using gates of said N-channel MOSFET and said P-channel double-diffused MOSFET as a mask; forming oxide films on side walls of individual gates of the N-channel MOSFET, a P-channel MOSFET constructing said CMOSFET and the P-channel double-diffused MOSFET; forming source-drain regions with an LDD structure of said N-channel MOSFET and an N + base contact regions of said P-channel double-diffused MOSFET by implanting a second dopant using the gates of said P-channel double-diffused MOSFET as a mask; forming source-drain regions of said P-channel MOSFET and source-drain regions of said P-channel double-diffused MOSFET by implanting a third dopant using the gates of said P-channel MOSFET an said P-channel double-diffused MOSFET and the oxide film formed on its side walls thereof as a mask.
Claim 8
Independent Claim
177 words
A method for producing a semiconductor device having a CMOSFET and a P-channel double-diffused MOSFET in a same semiconductor substrate, comprising the steps of: forming an N - regions for preparing an LDD structure in an N-channel MOSFET constructing said CMOSFET and N base regions of said P-channel double-diffused MOSFET by implanting a first dopant using gates of said N-channel MOSFET and said P-channel double-diffused MOSFET as a mask; forming oxide films on side walls of individual gates of the N-channel MOSFET, a P-channel MOSFET constructing said CMOSFET and the P-channel double-diffused MOSFET; forming source-drain regions with an LDD structure of said N-channel MOSFET and an N + base contact regions of said P-channel double-diffused MOSFET by implanting a second dopant using the gates of said P-channel double-diffused MOSFET as a mask; forming source-drain regions of said P-channel MOSFET and source-drain regions of said P-channel double-diffused MOSFET by implanting a third dopant using the gates of said P-channel MOSFET an said P-channel double-diffused MOSFET and the oxide film formed on its side walls thereof as a mask.
Claim 9
Dependent Claim
36 words
A method as claimed in claim 6, further comprising the step of selectively introducing said first dopant to form an N base contact region partly overlapping with the N base region of said P-channel double-diffused MOSFET.
References Cited (Backward Citations)
US4887142A
Cited
US4878096A
Cited
US5108944A
Cited
US5237193A
Cited
US5156989A
Cited
US4945070A
Cited
US5256582A
Cited
US5045492A
Cited
US5171699A
Cited
US5220218A
Cited
US5242841A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-08-22 | 1998-02-21 | 1998-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-08-22 | 2002-02-21 | 2002-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-08-22 | 2006-02-21 | 2006-08-23 | $7700.00 | Window Closed / Lapsed |