CMOS sidewall oxide-lightly doped drain process

Claim 1

A method for fabrication of a CMOS device, comprising the steps of: (a) providing a semiconductor substrate; (b) defining moat regions at the surface of said substrate; (c) introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; (d) forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations: (e) introducing a light dose of N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; (f) depositing a conformal oxide overall; (g) providing a patterned mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said P-channel locations, then introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; (h) depositing a patterned masking layer to cover a plurality of said P-channel device locations, anisotropically etching said conformal oxide over said N-type device locations to leave sidewall oxides at the sidewalls of said gates over said N-type device locations, and implanting a high dose of an N-type impurity to form N-type sources and drains, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective channel locations thereof; and (i) connecting said respective source/drain and gates to provide a desired circuit function; wherein all of step (e) is performed before (g), and all of step (g) is performed before step (h).

Claim 2

A method for fabrication of a CMOS device, comprising the steps of: (a) providing a semiconductor substrate; (b) defining moat regions at the surface of said substrate; (c) introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; (d) forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations: (e) introducing a light dose of N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; (f) depositing a conformal oxide overall; (g) providing a patterned mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said P-channel locations, then introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; (h) depositing a patterned masking layer to cover a plurality of said P-channel device locations, anisotropically etching said conformal oxide over said N-type device locations to leave sidewall oxides at the sidewalls of said gates over said N-type device locations, and implanting a high dose of an N-type impurity to form N-type sources and drains, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective channel locations thereof; and (i) connecting said respective source/drain and gates to provide a desired circuit function; wherein all of step (e) is performed before (g), and all of step (g) is performed before step (h).

Claim 4

A method for fabrication of a CMOS device, comprising the steps of: (a) providing a semiconductor substrate; (b) defining moat regions at the surface of said substrate; (c) introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; (d) forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations; (e) introducing a light dose of an N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; p1 depositing a conformal oxide overall; (f) providing a patterned first mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said P-channel locations then introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; (g) anisotropically etching said conformal oxide exposed by the removal of said first mask layer to leave sidewall oxides at the sidewalls of said gate layer over said N-channel device locations; (h) depositing a patterned second masking layer to cover a plurality of said P-channel device locations, and implanting a high dose of an N-type impurity to form N-type sources ad drains and removing said second masking layer, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof; and (i) connecting said respective source/drain and gates to provide a desired circuit function; wherein all of step (e) is performed before step (f), and all of step (f) is performed before step (h).

Claim 5

A method for fabrication of a CMOS device, comprising the steps of: (a) providing a semiconductor substrate; (b) defining moat regions at the surface of said substrate; (c) introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; (d) forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations; (e) introducing a light dose of an N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; p1 depositing a conformal oxide overall; (f) providing a patterned first mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said P-channel locations then introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; (g) anisotropically etching said conformal oxide exposed by the removal of said first mask layer to leave sidewall oxides at the sidewalls of said gate layer over said N-channel device locations; (h) depositing a patterned second masking layer to cover a plurality of said P-channel device locations, and implanting a high dose of an N-type impurity to form N-type sources ad drains and removing said second masking layer, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof; and (i) connecting said respective source/drain and gates to provide a desired circuit function; wherein all of step (e) is performed before step (f), and all of step (f) is performed before step (h).

Claim 6

A method for fabrication of a CMOS device, comprising the steps of: providing a semiconductor substrate; defining moat regions at the surface of said substrate; introducing impurities of a first conductivity type into selected portions of said substrate to form a plurality of tank regions; forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both first device locations and second device locations; introducing a light dose of a dopant of said first conductivity type into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; depositing conformal oxide overall; anisotropically etching said conformal oxide to form gate sidewalls of said conformal oxide on said first device locations; providing a patterned first mask layer to cover the locations of said first devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said second device locations, then introducing a heavy dose if impurities of a second conductivity type to form second conductivity type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; then depositing a patterned second masking layer to cover a plurality of said second device locations, implanting a high dose of an impurity of said conductivity type to form first conductivity type sources and drains and removing said second masking layer, whereby said first devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof; and connecting said respective source/drain and gates to provide a desired circuit function.

Claim 7

A method for fabrication of a CMOS device, comprising the steps of: providing a semiconductor substrate; defining moat regions at the surface of said substrate; introducing impurities of a first conductivity type into selected portions of said substrate to form a plurality of tank regions; forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both first device locations and second device locations; introducing a light dose of a dopant of said first conductivity type into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; depositing conformal oxide overall; anisotropically etching said conformal oxide to form gate sidewalls of said conformal oxide on said first device locations; providing a patterned first mask layer to cover the locations of said first devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not present at the sidewalls of said gates over said second device locations, then introducing a heavy dose if impurities of a second conductivity type to form second conductivity type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; then depositing a patterned second masking layer to cover a plurality of said second device locations, implanting a high dose of an impurity of said conductivity type to form first conductivity type sources and drains and removing said second masking layer, whereby said first devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof; and connecting said respective source/drain and gates to provide a desired circuit function.

Claim 8

A method for fabrication of a CMOS device, comprising the steps of: providing a semiconductor substrate; defining moat regions at the surface of said substrate; introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations; introducing a light dose of an N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; depositing a conformal oxide overall; anisotropically etching said conformal oxide layer to form gate sidewalls of said conformal oxide on said N-channel device locations; providing a first patterned mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not preset at the sidewalls of said gates over said second device locations, the introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; and then depositing a second patterned masking layer to cover a plurality of said P-channel device locations, implanting a high dose of an N-type impurity to form N-type sources and drains and removing said second masking layer, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof.

Claim 9

A method for fabrication of a CMOS device, comprising the steps of: providing a semiconductor substrate; defining moat regions at the surface of said substrate; introducing N-type impurities into selected portions of said substrate to form a plurality of N-tank regions; forming an insulated conductive gate layer over portions of said substrate to define a predetermined plurality of device locations within said moat regions, said device locations comprising both N-channel device locations and P-channel device locations; introducing a light dose of an N-type dopant into a shallow depth of said substrate surface overall, both in desired locations of lightly doped drain extension regions and in other locations; depositing a conformal oxide overall; anisotropically etching said conformal oxide layer to form gate sidewalls of said conformal oxide on said N-channel device locations; providing a first patterned mask layer to cover the locations of said N-channel devices, removing said conformal oxide where not covered by said masking layer, such that oxide is not preset at the sidewalls of said gates over said second device locations, the introducing a heavy dose of P-type impurities to form P-type source/drain regions in predetermined locations where the surface of said substrate is exposed, and removing said first masking layer; and then depositing a second patterned masking layer to cover a plurality of said P-channel device locations, implanting a high dose of an N-type impurity to form N-type sources and drains and removing said second masking layer, whereby said N-channel devices comprise a lightly doped drain extension region separating said respective source/drain regions thereof from said respective channel regions thereof.