US5648661A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the dies
Assignee: LSI Corp
•
Filing: 1994-09-14
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Granted: 1997-07-15
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Expires: 2014-09-14
Abstract
Abstract Unsingulated dies on a wafer may be individually electronically selected using various "electronic mechanisms" on the wafer. Conductive lines extend on the wafer from the electronic mechanism to the individual dies. The conductive lines may be provided in sets of two or more, such as for providing discrete power and ground connections from the external equipment to the individual dies. Redundant conductive lines may be provided to ensure against "open" faults. Diode and/or fuses may also be provided in conjunction with the conductive lines to ensure against leakages and shorts. Redundant electronic selection mechanisms may also be provided.
Inventors
- 👤 Michael D. Rostoker
- 👤 Carlos Dangelo
- 👤 James Koford
- 👤 Edwin Fulcher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G11; G11C; G11C29/00; G11C29/006; H; H10; H10D; H10D89/00; H10D89/10; G01R31/282; G01R31/2831; G01R31/2851; G01R31/2884; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5453
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
163 words
An integrated circuit wafer, comprising: a plurality of unsingulated dies formed on die sites formed by scribe lines on the wafer respectively; a plurality of electronic switches provided on the die sites respectively, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; a test signal line that is commonly connected to the test signal inputs of the electronic switches; an address signal line that is commonly connected to the address signal inputs of the decoders; and an address signal generator for applying a multi-bit address signal having a plurality of unique values corresponding to the decoders respectively to the address signal line, each decoder responding to the address signal of the unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch, the address signal generator comprising a counter, a count of which constitutes the address signal.
Claim 2
Dependent Claim
163 words
An integrated circuit wafer, comprising: a plurality of unsingulated dies formed on die sites formed by scribe lines on the wafer respectively; a plurality of electronic switches provided on the die sites respectively, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; a test signal line that is commonly connected to the test signal inputs of the electronic switches; an address signal line that is commonly connected to the address signal inputs of the decoders; and an address signal generator for applying a multi-bit address signal having a plurality of unique values corresponding to the decoders respectively to the address signal line, each decoder responding to the address signal of the unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch, the address signal generator comprising a counter, a count of which constitutes the address signal.
Claim 3
Dependent Claim
27 words
A wafer as in claim 1, in which the counter has a count input, and counts in response to an e-beam signal applied to the count input.
Claim 4
Dependent Claim
177 words
A testing system for an integrated circuit wafer having a plurality of unsingulated dies formed on die sites respectively, wherein said die sites are defined by scribe lines extending across the wafer, the testing system comprising: a plurality of electronic switches provided on the die sites respectively, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; a test signal line that is commonly connected to the test signal inputs of the electronic switches; an address signal line that is commonly connected to the address signal inputs of the decoders; and an address signal generator for applying a multi-bit address signal having a plurality of unique values corresponding to the decoders respectively to the address signal line, each decoder responding to the address signal of the unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch, the address signal generator comprising a counter, a count of which constitutes the address signal.
Claim 5
Dependent Claim
177 words
A testing system for an integrated circuit wafer having a plurality of unsingulated dies formed on die sites respectively, wherein said die sites are defined by scribe lines extending across the wafer, the testing system comprising: a plurality of electronic switches provided on the die sites respectively, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; a test signal line that is commonly connected to the test signal inputs of the electronic switches; an address signal line that is commonly connected to the address signal inputs of the decoders; and an address signal generator for applying a multi-bit address signal having a plurality of unique values corresponding to the decoders respectively to the address signal line, each decoder responding to the address signal of the unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch, the address signal generator comprising a counter, a count of which constitutes the address signal.
Claim 6
Dependent Claim
28 words
A testing system as in claim 3, in which the counter has a count input, and counts in response to an e-beam signal applied to the count input.
Claim 7
Independent Claim
196 words
A method of individually testing a plurality of unsingulated dies formed on respective die sites of an integrated circuit wafer, wherein said die sites are defined by scribe lines extending across the wafer, comprising the steps of: (a) providing a plurality of electronic switches on the die sites, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; (b) providing a test signal line that is commonly connected to the test signal inputs of the electronic switches; (c) providing an address signal line that is commonly connected to the address signal inputs of the decoder; (d) providing an address signal generator for applying a multi-bit address signal to the address signal line; (e) applying a test signal to the test signal line using a wire bond; and (f) controlling the address signal generator to sequentially generate the address signal as having a plurality of unique values corresponding to the decoders respectively, each decoder responding to the address signal of its unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch.
Claim 8
Independent Claim
196 words
A method of individually testing a plurality of unsingulated dies formed on respective die sites of an integrated circuit wafer, wherein said die sites are defined by scribe lines extending across the wafer, comprising the steps of: (a) providing a plurality of electronic switches on the die sites, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; (b) providing a test signal line that is commonly connected to the test signal inputs of the electronic switches; (c) providing an address signal line that is commonly connected to the address signal inputs of the decoder; (d) providing an address signal generator for applying a multi-bit address signal to the address signal line; (e) applying a test signal to the test signal line using a wire bond; and (f) controlling the address signal generator to sequentially generate the address signal as having a plurality of unique values corresponding to the decoders respectively, each decoder responding to the address signal of its unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch.
Claim 9
Independent Claim
207 words
A method of individually testing a plurality of unsingulated dies formed on respective die sites on an integrated circuit wafer, wherein said die sites are defined by scribe lines extending across the wafer, comprising the steps of: (a) providing a plurality of electronic switches on the die sites, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; (b) providing a test signal line that is commonly connected to the test signal inputs of the electronic switches; (c) providing an address signal line that is commonly connected to the address signal inputs of the decoder; (d) providing an address signal generator for applying a multi-bit address signal to the address signal line, the address signal generator comprising a counter, a count of which constitutes the address signal; (e) applying a test signal to the test signal line; and (f) causing the counter to count, thereby sequentially generating the address signal as having a plurality of unique values corresponding to the decoders respectively, each decoder responding to the address signal of its unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch.
Claim 10
Independent Claim
207 words
A method of individually testing a plurality of unsingulated dies formed on respective die sites on an integrated circuit wafer, wherein said die sites are defined by scribe lines extending across the wafer, comprising the steps of: (a) providing a plurality of electronic switches on the die sites, each switch having a test signal input, a test signal output that is connected to the die, and an address decoder having an address input; (b) providing a test signal line that is commonly connected to the test signal inputs of the electronic switches; (c) providing an address signal line that is commonly connected to the address signal inputs of the decoder; (d) providing an address signal generator for applying a multi-bit address signal to the address signal line, the address signal generator comprising a counter, a count of which constitutes the address signal; (e) applying a test signal to the test signal line; and (f) causing the counter to count, thereby sequentially generating the address signal as having a plurality of unique values corresponding to the decoders respectively, each decoder responding to the address signal of its unique value by causing the test signal output to be connected to the test signal input of the respective electronic switch.
Claim 11
Dependent Claim
47 words
A method as in claim 6, in which: step (d) comprises providing the counter as having a count input, and counts in response to an e-beam signal applied to the count input; and step (f) comprises applying the e-beam signal to the count input of the counter.
Claim 12
Independent Claim
148 words
A method of individually communicating signals to unsingulated dies on a semiconductor wafer, wherein said dies are defined by scribe lines extending across the wafer, comprising: defining a plurality of individual dies on a semiconductor wafer with scribe lines extending across the wafer, each die occupying a distinct area on the wafer; providing on each die, within the area of the die, an address decoding circuit associated with the die, each address decoding circuit being responsive to a unique address at a multi-bit address input of the address decoding circuit to connect power to the die with which it is associated; providing a multi-bit address signal in common to the multi-bit address input of each of the address decoder circuits; and selectively addressing and communicating signals to the individual dies by providing the unique address to which their associated address decoding circuit respond via the multi-bit address signal.
Claim 13
Independent Claim
148 words
A method of individually communicating signals to unsingulated dies on a semiconductor wafer, wherein said dies are defined by scribe lines extending across the wafer, comprising: defining a plurality of individual dies on a semiconductor wafer with scribe lines extending across the wafer, each die occupying a distinct area on the wafer; providing on each die, within the area of the die, an address decoding circuit associated with the die, each address decoding circuit being responsive to a unique address at a multi-bit address input of the address decoding circuit to connect power to the die with which it is associated; providing a multi-bit address signal in common to the multi-bit address input of each of the address decoder circuits; and selectively addressing and communicating signals to the individual dies by providing the unique address to which their associated address decoding circuit respond via the multi-bit address signal.
Claim 14
Dependent Claim
124 words
A method of individually communicating signals to unsingulated dies on a semiconductor wafer, according to claim 8 further comprising: defining on the wafer a first area and a second area, the first area being distinct and separate form the second area, the first area including the areas of the individual dies; providing first pads in the second area on the wafer; connecting said first pads, with first conductive lines on the wafer, to the multi-bit address input of the address decoder circuit; providing second pads in the second area of the wafer; connecting the second pads, with second conductive lines on the wafer, to the individual dies; connecting a multi-bit address signal to said first pads; and providing the signals through the second pads.
Claim 15
Dependent Claim
33 words
A method of individually communicating signals to unsingulated dies on a semiconductor wafer, according to claim 8, further comprising: providing redundant electronic mechanisms, on the wafer, for communicating signals to selected individual dies.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |