US5498886A
Expired / Lapsed
US
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Circuit module redundancy architecture
Assignee: Peraso Inc
•
Filing: 1994-05-20
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Granted: 1996-03-12
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Expires: 2014-05-20
Abstract
Abstract A system and method for wafer scale integration optimized for medium die size integrated circuits by interconnecting a large number of separate memory (or other circuit) modules on a semiconductor wafer so as to electrically exclude both defective modules and defective interconnect/power segments, and include operative modules and interconnect/power segments. A set of discretionary connections are associated with each of the separate modules and interconnect/power segments and such connections are made (or broken) after a module or interconnect or power segment is tested. A power supply network is set up by combining operative power segments. A bidirectional bus is set up by combining operative interconnect segments to connect to each operative modules. This bidirectional bus consists of one or more hierarchies for speed, power and yield considerations. Each module is assigned an identity code using discretionary connections.
Inventors
- 👤 Fu-Chieh Hsu
- 👤 Wingyu Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:14
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G11C29/832; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/202; G06F11/2051; G06F12/00; G06F12/02; G06F12/06; G06F12/0646; G06F12/0653; G06F12/0661; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068; G06F13/4072; G06F13/4077; G11C29/006; G11C29/04; G11C29/08; G11C29/48; G11C29/76; G11C29/80; G11C29/808; G11C29/88; H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G06F11/2023; G06F11/2028; H10D; H10D89/00
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
64 words
A semiconductor circuit on a substrate comprising: at least one circuit block which includes a plurality of replaceable circuit modules, each including a software programmable identification circuit with a unique preset address code; and at least one redundant circuit module in the at least one circuit block, the redundant circuit module including a software programmable identification circuit programmable with a unique preset address code.
Claim 2
Dependent Claim
64 words
A semiconductor circuit on a substrate comprising: at least one circuit block which includes a plurality of replaceable circuit modules, each including a software programmable identification circuit with a unique preset address code; and at least one redundant circuit module in the at least one circuit block, the redundant circuit module including a software programmable identification circuit programmable with a unique preset address code.
Claim 3
Dependent Claim
34 words
The device of claim 1, further comprising means for changing the address code of the identification circuit of the redundant circuit module to the unique preset address code of a defective replaceable circuit module.
Claim 4
Dependent Claim
113 words
A semiconductor circuit on a substrate comprising: at least one circuit block; at least one redundant circuit module in the at least one circuit block, the redundant circuit module including a software programmable identification circuit having a unique preset identification code; and a plurality of replaceable circuit modules within the at least one circuit block, each replaceable circuit module being associated with a disable switch activated when the replaceable circuit module is to be replaced, at least one of the disable switches being reversible for testing the associated module, and each replaceable circuit module including a software programmable identification circuit having a unique preset identification code which identifies the corresponding replaceable circuit module.
Claim 5
Dependent Claim
113 words
A semiconductor circuit on a substrate comprising: at least one circuit block; at least one redundant circuit module in the at least one circuit block, the redundant circuit module including a software programmable identification circuit having a unique preset identification code; and a plurality of replaceable circuit modules within the at least one circuit block, each replaceable circuit module being associated with a disable switch activated when the replaceable circuit module is to be replaced, at least one of the disable switches being reversible for testing the associated module, and each replaceable circuit module including a software programmable identification circuit having a unique preset identification code which identifies the corresponding replaceable circuit module.
Claim 6
Dependent Claim
32 words
The device of claim 3 wherein the identification circuit of the redundant circuit module comprises a plurality of programmable memory elements for storing the identification code associated with the redundant circuit module.
Claim 7
Dependent Claim
14 words
The device of claim 3, wherein the disable switches are each a programmable element.
Claim 8
Dependent Claim
13 words
The device of claim 5, wherein the programmable element comprises an EPROM cell.
Claim 9
Dependent Claim
13 words
The device of claim 5, wherein the programmable element comprises an EEPROM cell.
Claim 10
Dependent Claim
14 words
The device of claim 5, wherein the programmable element comprises a flash EPROM cell.
Claim 11
Dependent Claim
23 words
The device of claim 3, wherein the identification circuit of each of the replaceable circuit modules comprises a plurality of programmable memory elements.
Claim 12
Dependent Claim
38 words
The device of claim 3, further comprising interconnect circuitry coupled to the redundant circuit module and the replaceable circuit modules, wherein the interconnect circuitry comprises a plurality of interconnect segments each including signal lines and redundant signal lines.
Claim 13
Dependent Claim
74 words
The device of claim 10, wherein a first line of an interconnect segment is connected to a first probe pad and a second line of the interconnect segment is connected to a second probe pad, wherein the device further comprises at least one transistor connecting the first and second lines, whereby testing of the first and second lines for open defects can be carried out by probing of said first and second probe pads.
Claim 14
Dependent Claim
45 words
The device of claim 10, wherein at least one of the interconnect segments is connected to a plurality of in-line probe pads, whereby testing of the interconnect circuitry for defects within and between the interconnect segments can be carried out by probing the probe pads.
Claim 15
Dependent Claim
36 words
The device of claim 3, further comprising means for changing the identification code of the identification circuit of the redundant circuit module to the identification code of the identification circuit of a defective replaceable circuit module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-12 | 1999-09-11 | 2000-03-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-12 | 2003-09-11 | 2004-03-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-12 | 2007-09-11 | 2008-03-12 | $7700.00 | Window Closed / Lapsed |