US5446395A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test circuit for large scale integrated circuits on a wafer
Assignee: NEC Corp
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Filing: 1993-09-21
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Granted: 1995-08-29
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Expires: 2013-09-21
Abstract
Abstract A test circuit for conducting a simultaneous test of a plurality of integrated circuits provided in dicing regions of a wafer. The test circuit has a pattern generator electrically connected to the integrated circuits through first interconnections for generating input signal patterns and subsequent transmission thereof to each of the integrated circuits and pattern compressor/comparator electrically connected to the integrated circuits through second interconnections for analyzing output signals fetched from the integrated circuits so as to conduct a simultaneous test of a plurality of the integrated circuits.
Inventors
- 👤 Junichi Goto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 12:05
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/2851; G01R31/2884; G01R31/318511
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
149 words
A circuit for simultaneously testing at least two of a plurality of integrated circuits provided in dicing regions of a wafer comprising: an input test signal generating and transmitting means electrically connected to at least two of said plurality of integrated circuits through first interconnection means for generating input test signal patterns and for subsequently transmitting said input test signal patterns to each of said at least two integrated circuits; and output test signal analyzing means directly electrically connected to each of said at least two integrated circuits through second interconnection means for analyzing output test signals output from each of said at least two integrated circuits in response to said input test signal patterns so as to conduct a test of each of said at least two integrated circuits simultaneously, a number of said analyzing means being equal to a number of integrated circuits to be simultaneously tested.
Claim 2
Dependent Claim
149 words
A circuit for simultaneously testing at least two of a plurality of integrated circuits provided in dicing regions of a wafer comprising: an input test signal generating and transmitting means electrically connected to at least two of said plurality of integrated circuits through first interconnection means for generating input test signal patterns and for subsequently transmitting said input test signal patterns to each of said at least two integrated circuits; and output test signal analyzing means directly electrically connected to each of said at least two integrated circuits through second interconnection means for analyzing output test signals output from each of said at least two integrated circuits in response to said input test signal patterns so as to conduct a test of each of said at least two integrated circuits simultaneously, a number of said analyzing means being equal to a number of integrated circuits to be simultaneously tested.
Claim 3
Dependent Claim
24 words
The circuit as claimed in claim 1, wherein said test circuit is provided outside said dicing regions in which said integrated circuits are provided.
Claim 4
Dependent Claim
47 words
The circuit as claimed in claim 1, further comprising clock signal generating and transmission means connected to said at least two integrated circuits through third interconnections means for generating clock signals and for subsequently transmitting said clock signals to each of said at least two integrated circuits.
Claim 5
Dependent Claim
54 words
The circuit as claimed in claim 1, wherein said analyzing means comprise means for compressing a time series of said output signal patterns output from each of said at least two integrated circuits and means for comparing said compressed signals with expected values to determine whether said compressed signals and said expected values match.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-28 | 1999-02-27 | 1999-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-28 | 2003-02-27 | 2003-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-28 | 2007-02-27 | 2007-08-29 | $7700.00 | Window Closed / Lapsed |