US5591992A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electrostatic discharge protection in integrated circuits, systems and methods
Assignee: Texas Instruments Inc
•
Filing: 1995-06-07
•
Granted: 1997-01-07
•
Expires: 2015-06-07
Abstract
Abstract An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.
Inventors
- 👤 Jerald G. Leach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:48
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/711; H10D89/713; Y; Y10; Y10S; Y10S148/00; Y10S148/011
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
99 words
An electrostatic discharge protection circuit for use in an integrated circuit having bond pads and internal circuitry on a substrate for operation of the integrated circuit, the electrostatic discharge protection circuit comprising: a latchable circuit fabricated on said substrate and connected to a first said bond pad; and field effect transistors having connections to a second said bond pad, the field effect transistors located in proximity to said latchable circuit so that upon occurrence of an electrostatic discharge event the field effect transistors inject current into the substrate to latch said latchable circuit and thereby protect said integrated circuit.
Claim 2
Dependent Claim
99 words
An electrostatic discharge protection circuit for use in an integrated circuit having bond pads and internal circuitry on a substrate for operation of the integrated circuit, the electrostatic discharge protection circuit comprising: a latchable circuit fabricated on said substrate and connected to a first said bond pad; and field effect transistors having connections to a second said bond pad, the field effect transistors located in proximity to said latchable circuit so that upon occurrence of an electrostatic discharge event the field effect transistors inject current into the substrate to latch said latchable circuit and thereby protect said integrated circuit.
Claim 3
Dependent Claim
28 words
The circuit of claim 1 wherein said latchable circuit comprises an SCR circuit and said field effect transistors have respective resistive connections to the first said bond pad.
Claim 4
Dependent Claim
54 words
The circuit of claim 1 wherein each of the field effect transistors has a gate and first and second semiconductive regions, the first region resisitively connected to said latchable circuit, and the second region connected to said second bond pad, the field effect transistors operative to trigger the latchable circuit for electrostatic discharge protection.
Claim 5
Dependent Claim
40 words
The circuit of claim 3 wherein the gate of each of the field effect transistors is connected to a signal line, whereby the field effect transistors act together as an output buffer and as a trigger for the latchable circuit.
Claim 6
Dependent Claim
26 words
The circuit of claim 3 wherein the resistive connection of the first region of each of the field effect transistors is to the first bond pad.
Claim 7
Dependent Claim
125 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a tank region of a second conductivity type formed within said substrate; a first doped region of said second conductivity type formed within said tank region; a second doped region of said first conductivity type formed within said tank region adjacent said first doped region; a third doped region of said second conductivity type formed within said tank region spaced from said second doped region; and field effect transistors formed within said substrate spaced from said tank region, each of said field effect transistors comprising first and second source/drain regions of said second conductivity type spaced by a channel region wherein said first source/drain regions are resistively coupled to said third doped region.
Claim 8
Dependent Claim
125 words
A semiconductor device comprising: a semiconductor substrate of a first conductivity type; a tank region of a second conductivity type formed within said substrate; a first doped region of said second conductivity type formed within said tank region; a second doped region of said first conductivity type formed within said tank region adjacent said first doped region; a third doped region of said second conductivity type formed within said tank region spaced from said second doped region; and field effect transistors formed within said substrate spaced from said tank region, each of said field effect transistors comprising first and second source/drain regions of said second conductivity type spaced by a channel region wherein said first source/drain regions are resistively coupled to said third doped region.
References Cited (Backward Citations)
US2655610A
Cited
DE2336287A1
Cited
US4302875A
Cited
US4117507A
Cited
US4282555A
Cited
US4400711A
Cited
US4484244A
Cited
US4605872A
Cited
US4500845A
Cited
US4692781B2
Cited
US4692781A
Cited
US4692781B1
Cited
US4626882A
Cited
US4630162A
Cited
US4821096A
Cited
US4760433A
Cited
US5012317A
Cited
US4808861A
Cited
US5077591A
Cited
US5008724A
Cited
US5060037A
Cited
US5019888A
Cited
US4928023A
Cited
US4937639A
Cited
US4855620A
Cited
DD273722A1
Cited
US4939616A
Cited
US4922371A
Cited
US4896243A
Cited
US5036215A
Cited
US5465189A
Cited
US5072273A
Cited
US5140401A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |