Output buffer with enhanced electrostatic discharge protection

Claim 2

A CMOS output buffer with enhanced electrostatic discharge protection formed in a semiconductor surface on a substrate, comprising: a. an N-channel transistor having a source connected to a first reference supply, a drain connected to an output pad of the output buffer, and a gate connected to an input of the output buffer; b. a P-channel transistor formed in a first N-type region of said surface, including a source connected to a second reference supply, a drain connected to said output pad of the output buffer and a gate connected to another input of the output buffer, said P-channel source being formed of plural elongate diffusions and said P-channel drain being formed of plural elongate diffusions on both long sides of said P-channel source diffusions to form channel regions; and c. plural, separate diffusion regions each formed in said semiconductor surface on a side of said P-channel drain diffusions opposite said P-channel source diffusions, said plural diffusion regions each being connected to said second reference supply to furnish electrostatic discharge protection of said N-channel transistor.

Claim 3

The buffer of claim 1 in which said diffusion regions are uniformly spaced from said P-channel drain diffusions.

Claim 4

The buffer of claim 1 in which there are two P-channel source diffusions, four P-channel drain diffusions and three diffusion regions.

Claim 5

The buffer of claim 1 in which there is one diffusion region between two P-channel drain diffusions.

Claim 6

The buffer of claim 1 in which said diffusion regions extend only along the long side of each P-channel drain diffusion.

Claim 7

The buffer of claim 1 in which said P-channel source and drain diffusions and said diffusion regions each have substantially equal dimensions.

Claim 8

The buffer of claim 1 in which said P-channel source and drain diffusions and said P-channel drain diffusions and diffusion regions are closely spaced by about the same distance D.

Claim 9

The buffer of claim 1 in which said P-channel source and drain diffusions and said diffusion regions have long sides defined by about the same width W.

Claim 10

The buffer of claim 1 in which said P-channel drain diffusions and diffusion regions are uniformly separated by about a distance D, said P-channel drain diffusions and diffusion regions have long sides defined by about the same width W and the effective width Weff of said plural diffusion regions is much greater than said distance D.

Claim 11

The buffer of claim 9 in which said distance D has a ratio to said effective width Weff of about 1.5 to 1000.

Claim 12

The buffer of claim 10 in which said first N-type region of said surface has a sheet resistance of about 3000 ohms/square to effect a resistance between said P-channel drain diffusion and said diffusion region of about 4.5 ohms.

Claim 13

The buffer of claim 9 in which said effective width Weff is about four times the width W of one diffusion region.

Claim 14

The buffer of claim 11 in which said resistance is selected to result in a reverse bias voltage at said drain of said N-channel transistor that is less than the secondary breakdown voltage of said drain of said N-channel transistor during a positive polarity ESD event of about 6000 volts in a human body model.

Claim 15

The buffer of claim 1 in which said first N-type region is lightly doped and said P-channel source and drain diffusions and said diffusion regions are heavily doped.

Claim 16

The buffer of claim 1 in which said N-channel transistor is formed in a P-type region of said surface.

Claim 17

The buffer of claim 1 in which said first reference supply is V ss and said second reference supply is V dd .

Claim 18

The buffer of claim 1 in which said diffusion regions are heavily doped N-type and are formed in said N-type region.

Claim 19

The buffer of claim 1 in which said P-channel drain and source diffusions and said diffusion regions are substantially rectilinear.

Claim 20

A CMOS output buffer with enhanced electrostatic discharge protection formed in a semiconductor surface of a substrate, comprising: a. a first MOSFET transistor having a source connected to a first reference supply, a drain connected to an output pad of the output buffer and a gate connected to an input of the output buffer; b. a second MOSFET transistor having a source connected to a second reference supply, a drain connected to said output pad of the output buffer and a gate connected to another input of the output buffer; c. one of said first and second transistors being an N-channel transistor formed in a P-type region of said semiconductor and the other being a P-channel transistor being formed in an N-type region of said semiconductor; d. said second transistor having its source and drain formed of respective elongate source and drain diffusions uniformly and closely spaced alongside one another to form at least one channel region; and e. plural diffusion regions formed in said semiconductor surface on sides of said elongate drain diffusion opposite said elongate source diffusions, said diffusion regions and said elongate drain diffusions being uniformly and closely spaced from one another a distance D along a length defined as an effective width Weff, the material separating said diffusion regions and said elongate drain diffusions having a certain sheet resistance Rs, and said distance D, said effective width Weff and said sheet resistance Rs being selected to obtain a resistance Rc between said diffusion regions and elongate drain diffusions of no more than a certain value that, during a human body model electrostatic discharge event, results in a voltage across the drain and source of said second transistor that is less than the reverse bias breakdown voltage of the drain and source of the first transistor.

Claim 21

A CMOS output buffer with enhanced electrostatic discharge protection formed in a semiconductor surface of a substrate, comprising: a. a first MOSFET transistor having a source connected to a first reference supply, a drain connected to an output pad of the output buffer and a gate connected to an input of the output buffer; b. a second MOSFET transistor having a source connected to a second reference supply, a drain connected to said output pad of the output buffer and a gate connected to another input of the output buffer; c. one of said first and second transistors being an N-channel transistor formed in a P-type region of said semiconductor and the other being a P-channel transistor being formed in an N-type region of said semiconductor; d. said second transistor having its source and drain formed of respective elongate source and drain diffusions uniformly and closely spaced alongside one another to form at least one channel region; and e. plural diffusion regions formed in said semiconductor surface on sides of said elongate drain diffusion opposite said elongate source diffusions, said diffusion regions and said elongate drain diffusions being uniformly and closely spaced from one another a distance D along a length defined as an effective width Weff, the material separating said diffusion regions and said elongate drain diffusions having a certain sheet resistance Rs, and said distance D, said effective width Weff and said sheet resistance Rs being selected to obtain a resistance Rc between said diffusion regions and elongate drain diffusions of no more than a certain value that, during a human body model electrostatic discharge event, results in a voltage across the drain and source of said second transistor that is less than the reverse bias breakdown voltage of the drain and source of the first transistor.

Claim 22

The buffer of claim 19 in which said human body model presents 6000 volts through 1500 ohms and said certain value of resistance is about 4.85 ohms.

Claim 23

The buffer of claim 19 in which said distance D is about 1.5 micron, said effective width Weff is about 1000 microns and said sheet resistance R s is about 3000 ohms per square to obtain a certain value resistance R c of about 4.5 ohms.

Claim 24

The buffer of claim 19 in which said reverse bias breakdown voltage of the drain and source of the other transistor is about 20 volts.

Claim 25

The buffer of claim 19 in which said at least one transistor has plural elongate source diffusions and has plural elongate drain diffusions on both long sides of said elongate source diffusions, and there are plural elongate diffusion regions each on a side of said elongate drain diffusions opposite said elongate source diffusions.

Claim 26

The buffer of claim 19 in which there are two elongate source diffusions, four elongate drain diffusions and three diffusion regions.

Claim 27

The buffer of claim 19 in which said at least one transistor and at least one diffusion region are formed in N-type material.

Claim 28

The buffer of claim 19 in which said N-type material forms a well in P-type material.

Claim 29

The buffer of claim 17 in which said diffusions regions extend only along the long sides of said elongate drain diffusions.

Claim 30

The buffer of claim 19 in which said elongate source and drain diffusions and diffusion regions have substantially equal dimensions.

Claim 31

The buffer of claim 19 in which said distance D is substantially smaller than said effective width Weff by a ratio of about 1.5 to 1000.

Claim 32

The buffer of claim 19 in which said effective width Weff is about four times the length defined as a width W of one elongate diffusion regions.

Claim 33

The buffer of claim 19 in which said first reference supply is V dd and said second reference supply is V ss .

Claim 34

The buffer of claim 19 in which said elongate source and drain diffusions and said diffusion regions are substantially rectilinear.

Claim 35

The buffer of claim 19 in which said human body model electrostatic discharge event is of positive polarity.

Claim 36

The buffer of claim 19 in which said certain value of resistance R c obtains through selecting D, Weff and R s according to the following formula: R.sub.c =R.sub.s *(D/Weff)