Low voltage triggering semiconductor controlled rectifiers

Claim 2

An integrated circuit comprising: a device for which ESD protection is desired, said device including at least one MOS transistor; a lateral semiconductor controlled rectifier coupled to said device, said semiconductor controlled rectifier including a common region; a MOS-like structure integral with said semiconductor controlled rectifier, said MOS-like structure also including said common region, said semiconductor controlled rectifier being operable to be triggered by a current generated when said MOS-like structure is in avalanche breakdown.

Claim 3

The integrated circuit of claim 1 wherein said MOS-like structure has a trigger voltage equivalent to the breakdown voltage of a MOS transistor having the same insulator thickness and channel length as said MOS-like structure.

Claim 4

The integrated circuit of claim 1 wherein said integrated circuit comprises a dynamic random access memory integrated circuit chip.

Claim 5

The integrated circuit of claim 1 wherein said integrated circuit comprises a read only memory integrated circuit.

Claim 6

The integrated circuit of claim 1 wherein said integrated circuit comprises static random access memory integrated circuit.

Claim 7

The integrated circuit of claim 1 wherein said semiconductor controlled rectifier is formed in a semiconductor layer of a first conductivity type and includes: a first region of a second conductivity type formed within said semiconductor layer; a well region of said second conductivity type formed within said semiconductor layer and spaced from said first region; a gate region overlying said semiconductor layer between said first region and said well region; a second region of said first conductivity type formed within said well region.

Claim 8

The integrated circuit of claim 6 wherein said semiconductor controlled rectifier further includes a third region of said second conductivity type formed within said semiconductor layer spaced from said first region and partially overlapping said well region.

Claim 9

The integrated circuit of claim 7 wherein said MOS-like structure comprises said first and third regions and said gate overlying said semiconductor layer between said first and third regions, said gate separated from said semiconductor layer by a gate insulating layer.

Claim 10

The integrated circuit of claim 1 wherein said integrated circuit is formed within a semiconductor layer of a first conductivity type wherein: said semiconductor controlled rectifier comprises: a first doped region of a second conductivity type disposed in said semiconductor layer; a second doped region of said second conductivity type disposed in said semiconductor layer; a region of said semiconductor layer between said first and second doped regions; and a third doped region of said first conductivity type formed adjacent said second doped region; and wherein said MOS-like structure comprises: said first doped region of a second conductivity type disposed in said semiconductor layer; said second doped region of said second conductivity type disposed in said semiconductor layer; said region of said semiconductor layer between said first and second doped regions; said gate dielectric of substantially said selected thickness overlying said region of said semiconductor layer between said first and second doped regions; and a conductive gate overlying said gate dielectric.

Claim 11

The integrated circuit of claim 9 wherein said second doped region comprises a well region and a heavily doped region at least partially overlapping said well region, said heavily doped region adjacent said region of said semiconductor layer between said first and second doped regions and said third doped region formed within said well region.

Claim 12

The integrated circuit of claim 10 wherein said first conductivity type comprises p-type and said second conductivity type comprises n-type.

Claim 13

A silicon controlled rectifier comprising: a semiconductor layer, said semiconductor layer comprising silicon of a first conductivity type; at least two semiconductor regions in spaced apart relation formed in said semiconductor layer, said at least two semiconductor regions comprising silicon of a second conductivity type, said second conductivity type different than said first conductivity type; a gate formed over a region of said semiconductor layer between said semiconductor regions; a gate insulator interposed between said gate and said semiconductor layer; a well region of said second conductivity type formed in said semiconductor layer and at least partially overlapping a first of said at least two semiconductor regions; and third and fourth semiconductor regions formed in said well region, said third semiconductor region having said first conductivity type and said fourth semiconductor region having said second conductivity type.

Claim 14

A silicon controlled rectifier comprising: a semiconductor layer, said semiconductor layer comprising silicon of a first conductivity type; at least two semiconductor regions in spaced apart relation formed in said semiconductor layer, said at least two semiconductor regions comprising silicon of a second conductivity type, said second conductivity type different than said first conductivity type; a gate formed over a region of said semiconductor layer between said semiconductor regions; a gate insulator interposed between said gate and said semiconductor layer; a well region of said second conductivity type formed in said semiconductor layer and at least partially overlapping a first of said at least two semiconductor regions; and third and fourth semiconductor regions formed in said well region, said third semiconductor region having said first conductivity type and said fourth semiconductor region having said second conductivity type.

Claim 15

The semiconductor controlled rectifier of claim 12 and further comprising a plurality of diodes connected between a first voltage and a second voltage, a semiconductor package pad connected between at least two of said diodes.

Claim 16

A silicon controlled rectifier as recited in claim 8 wherein said gate insulating region comprises an oxide.

Claim 17

A semiconductor controlled rectifier comprising: a semiconductor layer of a first conductivity type; a first doped region of a second conductivity type formed in said semiconductor layer, said first conductivity type different than said second conductivity type; a second doped region of said second conductivity type formed in said semiconductor layer and spaced from said first doped region; a gate region formed overlying said semiconductor layer between said first and second doped regions; an insulating region formed between said gate and said semiconductor layer; a well region of said second conductivity type formed in said semiconductor layer and partially overlapping said second doped region; and a third doped region of said first conductivity type formed in said well region.

Claim 18

A semiconductor controlled rectifier comprising: a semiconductor layer of a first conductivity type; a first doped region of a second conductivity type formed in said semiconductor layer, said first conductivity type different than said second conductivity type; a second doped region of said second conductivity type formed in said semiconductor layer and spaced from said first doped region; a gate region formed overlying said semiconductor layer between said first and second doped regions; an insulating region formed between said gate and said semiconductor layer; a well region of said second conductivity type formed in said semiconductor layer and partially overlapping said second doped region; and a third doped region of said first conductivity type formed in said well region.

Claim 19

The semiconductor controlled rectifier of claim 15 wherein said first and second doped regions are self-aligned with said gate.

Claim 20

The semiconductor controlled rectifier recited in claim 15 and further comprising a pad coupled to said semiconductor controlled rectifier and to circuitry requiring protection from electrostatic discharge.

Claim 21

A semiconductor controlled rectifier as recited in claim 17 which further includes a resistor connected between said pad and said circuitry requiring electrostatic discharge protection.

Claim 22

The semiconductor controlled rectifier of claim 17 wherein said semiconductor package pad comprises an output pad.

Claim 23

The semiconductor controlled rectifier recited in claim 15 and further comprising a pad coupled to said semiconductor controlled rectifier and a connection to one of said semiconductor regions for contact to circuitry requiring electrostatic discharge protection.

Claim 24

The semiconductor controlled rectifier of claim 15 wherein said first doped region is electrically coupled to said gate region.

Claim 25

The semiconductor controlled rectifier of claim 15 and further comprising a contact region of said first conductivity type formed in said semiconductor layer, said contact region having a higher doping concentration than said semiconductor layer.

Claim 26

The semiconductor controlled rectifier of claim 15 and further comprising a fourth doped region of said second conductivity type formed in said well region.

Claim 27

The semiconductor controlled rectifier of claim 15 wherein said semiconductor layer of a first conductivity type comprises a p-doped silicon layer.

Claim 28

The semiconductor controlled rectifier of claim 15 and further comprising fourth and fifth doped regions of said second conductivity type formed within said well region, wherein said third doped region is disposed between said fourth and fifth doped regions.

Claim 29

The semiconductor controlled rectifier of claim 15 wherein said insulating region comprises an oxide.

Claim 30

The semiconductor controlled rectifier of claim 15 wherein said doped region and well region are electrically coupled to a contact pad.

Claim 31

The semiconductor controlled rectifier of claim 27 wherein said second doped region is coupled to a circuit to be protected from ESD.

Claim 32

The semiconductor controlled rectifier of claim 28 wherein said contact pad comprises an input pad.

Claim 33

The semiconductor controlled rectifier of claim 28 wherein said gate is electrically coupled to said first doped region and to said semiconductor layer.

Claim 34

The semiconductor controlled rectifier of claim 27 wherein said third region and said well region are also electrically coupled to a circuit to be protected from ESD.

Claim 35

The semiconductor controlled rectifier of claim 31 wherein said contact pad comprises an output pad.

Claim 36

The semiconductor controlled rectifier of claim 27 wherein said gate is coupled to a CMOS inverter.

Claim 37

A silicon controlled rectifier comprising: a first n-type silicon region; a first p-type silicon region adjacent said first n-type region; an insulating layer formed over said first p-type region; a gate formed over said insulating layer; a second n-type silicon region adjacent said first p-type region such that said first n-type region is spaced from said second n-type region by said first p-type region, said second n-type region comprising an n-doped region and an n-well region, said n-doped overlapping said n-well region; and a second p-type silicon region adjacent said second n-type region such that said first p-type region is spaced from said second p-type region by said second n-type region, said second p-type region formed within said n-well region.

Claim 38

A silicon controlled rectifier comprising: a first n-type silicon region; a first p-type silicon region adjacent said first n-type region; an insulating layer formed over said first p-type region; a gate formed over said insulating layer; a second n-type silicon region adjacent said first p-type region such that said first n-type region is spaced from said second n-type region by said first p-type region, said second n-type region comprising an n-doped region and an n-well region, said n-doped overlapping said n-well region; and a second p-type silicon region adjacent said second n-type region such that said first p-type region is spaced from said second p-type region by said second n-type region, said second p-type region formed within said n-well region.

Claim 39

A silicon controlled rectifier as recited in claim 13 wherein said first conductivity type comprises p-type and said second conductivity type comprises n-type.

Claim 40

The integrated circuit of claim 1 wherein said device for which ESD protection is desired includes at least one CMOS device.

Claim 41

The integrated circuit of claim 36 wherein said device for which ESD protection is desired includes an inverter.