US4821096A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Excess energy protection device
Assignee: Intel Corp
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Filing: 1985-12-23
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Granted: 1989-04-11
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Expires: 2005-12-23
Abstract
Abstract A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.
Inventors
- 👤 Timothy J. Maloney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
123 words
A protection device for protecting a semiconductor device from an excess event comprising: a first pnp lateral transistor having a collector and an emitter region of a first conductivity type, said emitter region being coupled to an input of said device, said transistor having a base region of a second conductivity type coupled to said input of said device, said collector region being coupled to ground; at least a second pnp lateral transistor having an emitter and a collector region of said first conductivity type, said emitter region being coupled through a resistor to said input, said transistor having a base region of second conductivity type, said collector region being coupled to ground; whereby said transistors dissipate power during an excess energy event.
Claim 2
Dependent Claim
123 words
A protection device for protecting a semiconductor device from an excess event comprising: a first pnp lateral transistor having a collector and an emitter region of a first conductivity type, said emitter region being coupled to an input of said device, said transistor having a base region of a second conductivity type coupled to said input of said device, said collector region being coupled to ground; at least a second pnp lateral transistor having an emitter and a collector region of said first conductivity type, said emitter region being coupled through a resistor to said input, said transistor having a base region of second conductivity type, said collector region being coupled to ground; whereby said transistors dissipate power during an excess energy event.
Claim 3
Dependent Claim
28 words
The protection device as described by claim 1 wherein said first transistor is formed in a well of a second conductivity type, said well coupled to said input.
Claim 4
Dependent Claim
17 words
The protection device as described by claim 2 wherein said second transistor is formed in said well.
Claim 5
Dependent Claim
23 words
The protection device as described by claim 2 wherein said second transistor is formed in a second well of a second conductivity type.
Claim 6
Dependent Claim
43 words
The protection device as described by claim 1 wherein said first and second transistors are formed on a silicon substrate, contacts to said emitter and collector regions of said transistors comprising a first conductive layer for raising the barrier height at said contacts.
Claim 7
Dependent Claim
15 words
The protection device as described by claim 5 wherein said first conductive layer comprises titanium.
Claim 8
Dependent Claim
15 words
The protection device as described by claim 5 wherein said first conductive layer comprises tungsten.
Claim 9
Dependent Claim
15 words
The protection device as described by claim 5 wherein a second conductive layer comprises aluminum.
Claim 10
Dependent Claim
105 words
A protection device for protecting a semiconductor device from an excess energy event comprising: a first transistor having a first region of a first conductivity type coupled to an input of said device, said first transistor having a second region of said first conductivity type coupled to ground; at least a second transistor having a third region of said first conductivity type coupled through a resistor to said input, said second transistor having a fourth region of said first conductivity type coupled to ground; said first transistor having a common gate with said second transistor; whereby said transistors dissipate power during an excess energy event.
Claim 11
Dependent Claim
105 words
A protection device for protecting a semiconductor device from an excess energy event comprising: a first transistor having a first region of a first conductivity type coupled to an input of said device, said first transistor having a second region of said first conductivity type coupled to ground; at least a second transistor having a third region of said first conductivity type coupled through a resistor to said input, said second transistor having a fourth region of said first conductivity type coupled to ground; said first transistor having a common gate with said second transistor; whereby said transistors dissipate power during an excess energy event.
Claim 12
Dependent Claim
14 words
The circuit of claim 9 wherein said first and second transistors comprise p-channel transistors.
Claim 13
Dependent Claim
17 words
The circuit of claim 9 wherein said first and second transistors are formed in a common well.
Claim 14
Dependent Claim
15 words
The circuit of claim 9 wherein said first and second transistors comprise pnp lateral transistors.
Claim 15
Dependent Claim
20 words
The circuit of claim 10 wherein said first region comprises a source region and said second comprises a drain region.
Claim 16
Dependent Claim
21 words
The circuit of claim 10 wherein said third region comprises a source region and said fourth region comprises a drain region.
Claim 17
Dependent Claim
21 words
The circuit of claim 12 wherein said first region comprises an emitter region and said second region comprises a collector region.
Claim 18
Dependent Claim
21 words
The circuit of claim 12 wherein said third region comprises an emitter region and said fourth region comprises a collector region.
Claim 19
Dependent Claim
26 words
The circuit of claim 9 wherein said first transistor is formed in a well of a second conductivity type, said well being coupled to said input.
Claim 20
Dependent Claim
14 words
The circuit of claim 17 wherein said second transistor is formed in said well.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-10 | 1992-10-10 | 1993-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-10 | 1996-10-10 | 1997-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-10 | 2000-10-10 | 2001-04-11 | $7700.00 | Window Closed / Lapsed |