Programmable attenuator

Claim 2

A programmable attenuator comprising: resistance means, wherein said resistance means is an elongated region of one conductivity type in a semiconductive layer of the opposite conductivity type; differential amplifier means having an output coupled to one terminal of said resistance means and a non-invering input coupled to a ground node; a plurality of switch means each coupled to said resistance means at one of a plurality of spaced apart locations along the length thereof, wherein said switch means are field-effect transistors, and wherein said region of said one conductivity type forms a first source/drain region of said field effect transistors; and means to selectively couple each of said switch means to an inverting input of said differential amplifier means, wherein the selection of each of said switch means causes a predetermined change in the gain of said differential amplifier means.

Claim 3

The attenuator of claim 1 wherein said elongated region has a serpentine configuration and said field-effect transistor means are arranged in an array of rows and columns interleaved therewith.

Claim 4

The attenuator of claim 2 wherein the width of said elongated region adjacent each of said field-effect transistor means is related to a predetermined incremental change in resistance of said resistance means.

Claim 5

The attenuator of claim 3 wherein said selective coupling means comprises row select means and column select means.

Claim 6

The attenuator of claim 4 wherein the gates of each column of field-effect transistor means are coupled together and to said column select means.

Claim 7

The attenuator of claim 5 wherein the second source/drain region of each row of field-effect transistor means are coupled together and to said row select means.

Claim 8

A programmable attenuator comprising: resistance means, wherein said resistance means is a region of one conductivity type in a semiconductor layer of the opposite conductivity type, and wherein said resistance means has a generally serpentine configuration; an array of rows and columns of field effect transistor switches interleaved with said resistance means, each of said transistor switches being coupled to said resistance means at one of a plurality of spaced apart locations along the length thereof, each of said locations dividing said resistance means into a first segment and a second segment, wherein the selection of each successive switch means causes a predetermined logarithmic change in the ratio of the resistance of said first segment to the resistance of said second segment, and wherein said region of said one conductivity type forms one source/drain region of each of said field-effect transistor switches; and row select means coupled to the output of each row of said transistor switches; and column select means coupled to the outputs of each column of each transistor switches.

Claim 9

A programmable attenuator comprising: resistance means, wherein said resistance means is a region of one conductivity type in a semiconductor layer of the opposite conductivity type, and wherein said resistance means has a generally serpentine configuration; an array of rows and columns of field effect transistor switches interleaved with said resistance means, each of said transistor switches being coupled to said resistance means at one of a plurality of spaced apart locations along the length thereof, each of said locations dividing said resistance means into a first segment and a second segment, wherein the selection of each successive switch means causes a predetermined logarithmic change in the ratio of the resistance of said first segment to the resistance of said second segment, and wherein said region of said one conductivity type forms one source/drain region of each of said field-effect transistor switches; and row select means coupled to the output of each row of said transistor switches; and column select means coupled to the outputs of each column of each transistor switches.

Claim 10

The attenuator of claim 7 wherein each column select means comprises the gates of said field-effect transistor means in one of said columns.

Claim 11

The attenuator of claim 8 wherein each row select means comprises the second source/drain regions of each of said field-effect transistor means in one of said rows.

Claim 12

The attenuator of claim 9 wherein the width of said region of said one conductivity type adjacent each of said field-effect transistor means is related to a predetermined incremental change in resistance of said resistance means.

Claim 13

The attenuator of claim 10, further including: differential amplifier means having inverting and noninverting inputs and an output, wherein said row select means are coupled to said inverting input, one terminal of said resistance means is coupled to said output, and said noninverting input is coupled to a ground node, and wherein said differential amplifier means output forms the output of said attenuator.

Claim 14

The attenuator of claim 11 wherein the incremental change in resistance of said resistance means between each successive field-effect transistor means causes a substantially equal change in the gain of said differential amplifier means.