Method of making complementary bipolar polysilicon emitter devices

Claim 1

A method for forming an integrated circuit structure including at least one bipolar transistor and at least one field effect (MOS) transistor on a common substrate comprising the steps of: defining buried layers within said substrate; forming bipolar doped intrinsic base regions within said substrate; depositing a single layer of polysilicon on said substrate; forming insulating isolation rings within said polysilicon layer around each region where an emitter is to be formed, each ring having an inside region and an outside region of polysilicon wherein the step of forming insulating isolation rings includes the step of etching ring-shaped slots within the polysilicon layer and filling the ring-shaped slots with an insulating material; without removing the insulating isolation rings, selectively forming self-aligned emitters within said substrate below said inside regions of polysilicon; selectively forming base contacting regions within said substrate below said outside regions of polysilicon; forming MOS gates; forming MOS source and drain regions; and providing surface contacts to said buried layers, emitters, base contacting regions, MOS gates, source, and drain regions.

Claim 2

A method for forming an integrated circuit structure including at least one bipolar transistor and at least one field effect (MOS) transistor on a common substrate comprising the steps of: defining buried layers within said substrate; forming bipolar doped intrinsic base regions within said substrate; depositing a single layer of polysilicon on said substrate; forming insulating isolation rings within said polysilicon layer around each region where an emitter is to be formed, each ring having an inside region and an outside region of polysilicon wherein the step of forming insulating isolation rings includes the step of etching ring-shaped slots within the polysilicon layer and filling the ring-shaped slots with an insulating material; without removing the insulating isolation rings, selectively forming self-aligned emitters within said substrate below said inside regions of polysilicon; selectively forming base contacting regions within said substrate below said outside regions of polysilicon; forming MOS gates; forming MOS source and drain regions; and providing surface contacts to said buried layers, emitters, base contacting regions, MOS gates, source, and drain regions.

Claim 9

A method for forming an integrated circuit structure including complementary bipolar transistors and complementary field effect (MOS) transistors on a common substrate comprising the steps of: providing a polished silicon substrate with defined buried collector regions therein and an epitaxial silicon layer thereon; depositing a first oxide layer on top of said epitaxial layer; photolithographically defining bipolar recessed regions and MOS recessed regions within said first oxide layer substantially through to said epitaxial layer; forming doped intrinsic base regions within said epitaxial layer just below said bipolar recessed regions; depositing a gate oxide layer on top of said first oxide layer and over all recessed regions; selectively and accurately removing portions of said gate oxide layer on top of said intrinsic base regions through a wet etch process; depositing a single layer of polysilicon thereon; photolithographically defining and etching narrow slots within said polysilicon layer in the form of rings surrounding each region where an emitter is to be formed; accurately filling said slots with an insulating dielectric material; selectively forming, through N-type doping, self-aligned NPN emitters and PNP base contacting regions; selectively forming, through P-type doping, self-aligned PNP emitters and NPN base contacting regions; photolithographically removing excess polysilicon from the periphery of the bipolar transistors and defining MOS polysilicon gates; forming, through doping, MOS source and drain regions; and forming contacts to emitters, base-containing regions and gates and to source, drain, and collector regions.

Claim 10

A method for forming an integrated circuit structure including complementary bipolar transistors and complementary field effect (MOS) transistors on a common substrate comprising the steps of: providing a polished silicon substrate with defined buried collector regions therein and an epitaxial silicon layer thereon; depositing a first oxide layer on top of said epitaxial layer; photolithographically defining bipolar recessed regions and MOS recessed regions within said first oxide layer substantially through to said epitaxial layer; forming doped intrinsic base regions within said epitaxial layer just below said bipolar recessed regions; depositing a gate oxide layer on top of said first oxide layer and over all recessed regions; selectively and accurately removing portions of said gate oxide layer on top of said intrinsic base regions through a wet etch process; depositing a single layer of polysilicon thereon; photolithographically defining and etching narrow slots within said polysilicon layer in the form of rings surrounding each region where an emitter is to be formed; accurately filling said slots with an insulating dielectric material; selectively forming, through N-type doping, self-aligned NPN emitters and PNP base contacting regions; selectively forming, through P-type doping, self-aligned PNP emitters and NPN base contacting regions; photolithographically removing excess polysilicon from the periphery of the bipolar transistors and defining MOS polysilicon gates; forming, through doping, MOS source and drain regions; and forming contacts to emitters, base-containing regions and gates and to source, drain, and collector regions.

Claim 18

A method for forming an integrated circuit structure including at least one bipolar transistor and at least one field effect (MOS) transistor on a common substrate comprising the steps of: defining buried layers within said substrate; forming bipolar doped intrinsic base regions within said substrate; depositing a single layer of polysilicon on said substrate; forming insulating isolation rings within said polysilicon layer around each region where an emitter is to be formed, each ring having an inside region and an outside region of polysilicon and including a ring-shaped slot filled with an insulating material; without removing the insulating isolation rings, selectively forming self-aligned emitters within said substrate below said inside regions of polysilicon; selectively forming base contacting regions within said substrate below said outside regions of polysilicon; forming MOS gates; forming MOS source and drain regions; forming a layer of a silicide compound on said polysilicon layer; and providing surface contacts to said buried layers, emitters, base contacting regions, MOS gates, source, and drain regions.

Claim 19

A method for forming an integrated circuit structure including at least one bipolar transistor and at least one field effect (MOS) transistor on a common substrate comprising the steps of: defining buried layers within said substrate; forming bipolar doped intrinsic base regions within said substrate; depositing a single layer of polysilicon on said substrate; forming insulating isolation rings within said polysilicon layer around each region where an emitter is to be formed, each ring having an inside region and an outside region of polysilicon and including a ring-shaped slot filled with an insulating material; without removing the insulating isolation rings, selectively forming self-aligned emitters within said substrate below said inside regions of polysilicon; selectively forming base contacting regions within said substrate below said outside regions of polysilicon; forming MOS gates; forming MOS source and drain regions; forming a layer of a silicide compound on said polysilicon layer; and providing surface contacts to said buried layers, emitters, base contacting regions, MOS gates, source, and drain regions.