US4497107A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making self-aligned high-frequency static induction transistor
Assignee: Verizon Laboratories Inc
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Filing: 1983-09-12
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Granted: 1985-02-05
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Expires: 2003-09-12
Abstract
Abstract A gate-source structure and fabrication method for a surface-gate static induction transistor. The method requires only one masking step during fabrication, thereby eliminating or minimizing mask registration problems during fabrication of the devices. The method and the device are characterized by a two-step etching process which forms T-shaped gate windows in layers of poly-crystalline silicon with different doping levels. The source region is formed during an annealing step from the layer with high doping level. During the annealing step, the gate regions are also formed from gate impurities implanted previously in the gate windows. The source structure and the gate structure are separated by a silicon dioxide protective layer.
Inventors
- 👤 Adrian I. Cogan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:21
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/012; H10D30/202
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
242 words
A method for forming a gate-source structure for a static induction transistor, said method comprising the steps of: growing a high resistivity expitaxial layer on a surface of a semiconductor substrate; depositing a highly doped layer of polycrystalline silicon on said expitaxial layer; depositing a lightly doped layer of polycrystalline silicon on said highly doped layer; forming a mask on said lightly doped layer with openings in said mask at predetermined gate window locations; etching by anistropic plasma at said window locations through said lightly doped layer and partially through said highly doped layer; etching by wet etching mix at said window locations through said highly doped region to the surface of said epitaxial layer, said wet etching mix having a higher etching rate in said highly doped layer than in said lightly doped layer; growing a silicon dioxide layer on the exposed surfaces of said epitaxial, highly doped and lightly doped layers; etching by reactive ions to remove said silicon dioxide layer from the horizontal surface of said lightly doped layer and from the unmasked surface of said epitaxial layer as defined by said window locations; implanting gate region impurities; annealing to form gate and source regions in said epitaxial layer by diffusion of dopant from said highly doped layer of polycrystalline silicon; etching to remove silicon dioxide formed during said annealing; and depositing metal over the entire surface to form gate and source electrodes without the need of a mask.
Claim 2
Independent Claim
242 words
A method for forming a gate-source structure for a static induction transistor, said method comprising the steps of: growing a high resistivity expitaxial layer on a surface of a semiconductor substrate; depositing a highly doped layer of polycrystalline silicon on said expitaxial layer; depositing a lightly doped layer of polycrystalline silicon on said highly doped layer; forming a mask on said lightly doped layer with openings in said mask at predetermined gate window locations; etching by anistropic plasma at said window locations through said lightly doped layer and partially through said highly doped layer; etching by wet etching mix at said window locations through said highly doped region to the surface of said epitaxial layer, said wet etching mix having a higher etching rate in said highly doped layer than in said lightly doped layer; growing a silicon dioxide layer on the exposed surfaces of said epitaxial, highly doped and lightly doped layers; etching by reactive ions to remove said silicon dioxide layer from the horizontal surface of said lightly doped layer and from the unmasked surface of said epitaxial layer as defined by said window locations; implanting gate region impurities; annealing to form gate and source regions in said epitaxial layer by diffusion of dopant from said highly doped layer of polycrystalline silicon; etching to remove silicon dioxide formed during said annealing; and depositing metal over the entire surface to form gate and source electrodes without the need of a mask.
Claim 3
Dependent Claim
34 words
A method as defined in claim 1 wherein said step of etching by wet etching mix etchs the window in said highly doped layer sufficiently to provide separation between the gate and source regions.
Claim 4
Dependent Claim
29 words
A method as defined in claim 2 wherein said gate regions are approximately one and one-half to two microns deep and said source region is about 0.2 micron deep.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |