Method for manufacturing vertical PNP transistor with shallow emitter

Claim 1

A process for forming a vertical PNP transistor having a high current gain exceeding about 200 and a high frequency response due to said transistor having a shallow, dislocation-free, P-type diffused emitter, said emitter further characterized by a steep concentration gradient, said process comprising the steps of: (a) providing a monocrystalline semiconductor silicon substrate having a subcollector region doped with a P-type impurity; (b) forming an N-type base region for said transistor in said substrate; (c) forming an insulator layer over said base region; (d) defining and forming an emitter window in said insulator layer exposing a planar surface region of said base region; (e) forming a polycrystalline silicon layer on said exposed planar surface of said base region; (f) doping said polycrystalline silicon layer with P-type impurities in a region adjacent to a desired emitter region to maintain a critical concentration of said P-type impurities at the interface between the polycrystalline silicon layer and the monocrystalline substrate below the concentration level of about 5×10 19 ions/cm 3 ; and (g) subjecting the resulting structure to conditions whereby the P-type doping ions contained in the polycrystalline silicon layer are controllably driven into the monocrystalline silicon forming an emitter region having a steep concentration gradient given by a concentration of P-type ions of at least 1×10 19 ions/cm 3 extending to a depth of at least 2000 Å and a concentration of less than about 1×1O 16 ions/cm 3 at a depth of about 3500 Å from the surface of the monocrystalline silicon without effecting dislocations in the monocrystalline silicon.