US4437897A
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US
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Fabrication process for a shallow emitter/base transistor using same polycrystalline layer
Assignee: International Business Machines Corp
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Filing: 1982-05-18
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Granted: 1984-03-20
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Expires: 2002-05-18
Abstract
Abstract A method for fabricating a high performance bipolar device having a shallow emitter and a narrow intrinsic base region is described. The method uses a minimum number of process steps. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A layer of polycrystalline silicon is deposited on the silicon substrate. The surface of the polycrystalline silicon is oxidized and the polycrystalline silicon is implanted with a base impurity. Silicon nitride and oxide layers are deposited on the polysilicon layer. An opening is made in the surface oxide layers and the silicon nitride layer to define the emitter area. The polycrystalline silicon is thermally oxidized to drive the base impurity into the substrate. The thermal oxide is removed in an isotropic etch to form a sidewall. The emitter impurity is ion implanted into the polycrystalline silicon in the emitter area and then driven into the substrate. The collector, base and emitter contact openings are made and the conductive metallurgy is formed.
Inventors
- 👤 Bernard M. Kemlage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:12
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/177; H10D10/00; H10D10/40; H10D10/441; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10P76/00; H10P76/40; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/92; Y10S438/965
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
220 words
A process for forming a transistor having a shallow emitter region and a narrow intrinsic base region and an extrinsic base region using the same polycrystalline silicon layer comprising the steps of depositing a layer of polycrystalline silicon on a semiconductor substrate provided with a subcollector, epitaxy, isolated regions, and oxide surface with holes open in the oxide surface for the extrinsic base, intrinsic base and emitter region, thermally oxidizing the surface of the polycrystalline silicon layer, implanting the base impurity into the polycrystalline silicon layer, defining and removing the surface oxide layer and the polycrystalline silicon layer from the subcollector reach-through area, depositing a silicon nitride layer, depositing a silicon dioxide layer, opening the silicon dioxide layer the silicon nitride layer and the thermal oxide layer to define the intrinsic base and the emitter area, thermally oxidizing the polycrystalline layer and driving the base impurity downwardly into the epitaxial layer to form the extrinsic base region and the intrinsic base region, etching the thermal oxide in the emitter area in an isotropic etch, ion implanting the emitter impurity into the emitter area of the polycrystalline silicon layer, thermally oxidizing to drive the emitter impurity inwardly into the epitaxial layer to form the emitter region, and opening the collector, extrinsic base and emitter contact openings and forming the conductive metallurgy.
Claim 2
Dependent Claim
220 words
A process for forming a transistor having a shallow emitter region and a narrow intrinsic base region and an extrinsic base region using the same polycrystalline silicon layer comprising the steps of depositing a layer of polycrystalline silicon on a semiconductor substrate provided with a subcollector, epitaxy, isolated regions, and oxide surface with holes open in the oxide surface for the extrinsic base, intrinsic base and emitter region, thermally oxidizing the surface of the polycrystalline silicon layer, implanting the base impurity into the polycrystalline silicon layer, defining and removing the surface oxide layer and the polycrystalline silicon layer from the subcollector reach-through area, depositing a silicon nitride layer, depositing a silicon dioxide layer, opening the silicon dioxide layer the silicon nitride layer and the thermal oxide layer to define the intrinsic base and the emitter area, thermally oxidizing the polycrystalline layer and driving the base impurity downwardly into the epitaxial layer to form the extrinsic base region and the intrinsic base region, etching the thermal oxide in the emitter area in an isotropic etch, ion implanting the emitter impurity into the emitter area of the polycrystalline silicon layer, thermally oxidizing to drive the emitter impurity inwardly into the epitaxial layer to form the emitter region, and opening the collector, extrinsic base and emitter contact openings and forming the conductive metallurgy.
Claim 3
Dependent Claim
18 words
A process as described in claim 1 whereby the layer of polycrystalline silicon is 1000Å to 5000Å thick.
Claim 4
Dependent Claim
41 words
A process as described in claim 1 wherein the said ion implanting of base impurities is boron with an average doping level of between about 1×10 18 to 1×10 21 atoms/cc and is mostly contained within the said polycrystalline silicon layer.
Claim 5
Dependent Claim
52 words
A process as described in claim 1 whereby the said polycrystalline silicon which forms the said intrinsic base and said emitter area is partially consumed by said thermal oxidation while the said extrinsic base area is protected by a thermal oxidation screen composed of silicon dioxide, silicon nitride and surface oxide layers.
Claim 6
Dependent Claim
49 words
A process as described in claim 4 whereby the said thermal oxidation of the said polycrystalline silicon in the said intrinsic base and emitter areas which drives the said base impurities downwardly into the said epitaxial layer is at a temperature of between about 800° C. to 1000° C.
Claim 7
Dependent Claim
38 words
A process as described in claim 1 wherein the resulting PN base-emitter junction is between about 100Å to 2000Å in depth into the said epitaxy and a portion of the said junction is within the said polycrystalline silicon.
Claim 8
Dependent Claim
25 words
A process as described in claim 1 wherein the resulting PN base-collector junction is between about 200Å to 4000Å in depth into the said epitaxy.
Claim 9
Dependent Claim
233 words
A process for forming a transistor having a shallow emitter region and a narrow intrinsic base region and an extrinsic base region using the same polycrystalline silicon layer comprising the steps of depositing a layer of polycrystalline silicon on a semiconductor substrate provided with a subcollector, epitaxy, isolated regions and oxide surface with holes open in the oxide surface for the extrinsic base, intrinsic base and emitter region, thermally oxidizing the surface of the polycrystalline silicon layer, implanting the base impurity into the polycrystalline silicon layer, defining and removing the surface oxide layer and the polycrystalline silicon layer from the subcollector reach-through area, depositing a silicon nitride layer, depositing a silicon dioxide layer, opening the silicon dioxide layer, the silicon nitride layer and the thermal oxide layer to define the intrinsic base and emitter area, thermally oxidizing the polycrystalline layer and driving the base impurity downwardly into the epitaxial layer to form the extrinsic base region and the intrinsic base region, etching the thermal oxide in the emitter area in an isotropic etch, depositing a silicon dioxide layer, etching the silicon dioxide layer in an isotropic etch, ion implanting the emitter impurity into the emitter area of the polycrystalline silicon layer, thermally oxidizing to drive the emitter impurity inwardly into the epitaxial layer to form the emitter region, and opening the collector, extrinsic base and emitter contact openings and forming the conductive metallurgy.
Claim 10
Dependent Claim
233 words
A process for forming a transistor having a shallow emitter region and a narrow intrinsic base region and an extrinsic base region using the same polycrystalline silicon layer comprising the steps of depositing a layer of polycrystalline silicon on a semiconductor substrate provided with a subcollector, epitaxy, isolated regions and oxide surface with holes open in the oxide surface for the extrinsic base, intrinsic base and emitter region, thermally oxidizing the surface of the polycrystalline silicon layer, implanting the base impurity into the polycrystalline silicon layer, defining and removing the surface oxide layer and the polycrystalline silicon layer from the subcollector reach-through area, depositing a silicon nitride layer, depositing a silicon dioxide layer, opening the silicon dioxide layer, the silicon nitride layer and the thermal oxide layer to define the intrinsic base and emitter area, thermally oxidizing the polycrystalline layer and driving the base impurity downwardly into the epitaxial layer to form the extrinsic base region and the intrinsic base region, etching the thermal oxide in the emitter area in an isotropic etch, depositing a silicon dioxide layer, etching the silicon dioxide layer in an isotropic etch, ion implanting the emitter impurity into the emitter area of the polycrystalline silicon layer, thermally oxidizing to drive the emitter impurity inwardly into the epitaxial layer to form the emitter region, and opening the collector, extrinsic base and emitter contact openings and forming the conductive metallurgy.
Claim 11
Dependent Claim
21 words
A process as described in claim 8 including the step of depositing a silicon nitride layer on said silicon dioxide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-03-20 | 1987-09-19 | 1988-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-03-20 | 1991-09-19 | 1992-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-03-20 | 1995-09-19 | 1996-03-20 | $7700.00 | Window Closed / Lapsed |