US4345366A
Expired / Lapsed
US
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Self-aligned all-n+ polysilicon CMOS process
Assignee: LSI Logic FSI Corp
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Filing: 1980-10-20
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Granted: 1982-08-24
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Expires: 2000-10-20
Abstract
Abstract Disclosed is a process for forming self-aligned all n + -doped polysilicon gates and interconnections in CMOS integrated circuits. Polysilicon is formed into the n-FET gate, a barrier for the p-FET region and the interconnect pattern. Then, arsenosilicate glass (ASG) is formed over the interconnect and the p-FET gate and N-FET active regions. The p-FET gate is etched using the ASG as a mask. The device is heated driving in impurities from the ASG to n + dope the polysilicon and form the n-FET source and drain. Then, boron is implanted in the p-FET source and drain regions.
Inventors
- 👤 Ronald W. Brower
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:42
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0186; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; H10P76/00; H10P76/20; H10W; H10W20/00; H10W20/01
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
200 words
In a process for forming an integrated circuit from a structure comprising a body of semiconductor material having a first active region of a first conductivity type, a second active region of the second conductivity type, a relatively thin silicon dioxide layer formed over said active regions, the improvement comprising: forming a first polysilicon gate over said first active region and a polysilicon layer over said second active region; forming a mask containing impurities of the second conductivity type over the structure and laterally encompassing the first active region and defining a gate region in the second active region; forming the polysilicon layer in the second active region to a second polysilicon gate defined by the mask; implanting the first-conductivity-type impurities in source and drain regions defined in the second active region by the mask; and diffusing the second-conductivity-type impurities from the mask into source and drain regions defined in the first active region by the first polysilicon gate and into both the first and second polysilicon gates; the combination of implantation and diffusion forming a self-aligned source and drain in each of the first and second active regions, and both polysilicon gates doped with said second conductivity type impurities.
Claim 2
Dependent Claim
200 words
In a process for forming an integrated circuit from a structure comprising a body of semiconductor material having a first active region of a first conductivity type, a second active region of the second conductivity type, a relatively thin silicon dioxide layer formed over said active regions, the improvement comprising: forming a first polysilicon gate over said first active region and a polysilicon layer over said second active region; forming a mask containing impurities of the second conductivity type over the structure and laterally encompassing the first active region and defining a gate region in the second active region; forming the polysilicon layer in the second active region to a second polysilicon gate defined by the mask; implanting the first-conductivity-type impurities in source and drain regions defined in the second active region by the mask; and diffusing the second-conductivity-type impurities from the mask into source and drain regions defined in the first active region by the first polysilicon gate and into both the first and second polysilicon gates; the combination of implantation and diffusion forming a self-aligned source and drain in each of the first and second active regions, and both polysilicon gates doped with said second conductivity type impurities.
Claim 3
Dependent Claim
203 words
A process for forming a CMOS integrated circuit from a structure comprising a body of n-type semiconductor material having a first and second active regions, respectively, with a p-well formed in the first active region, and a relatively thin silicon dioxide layer formed over said active regions, said process comprising: forming a first polysilicon gate over the silicon dioxide layer formed in said first active region and a polysilicon layer over the silicon dioxide layer in said second active region; forming a mask containing n-type impurities over the structure and laterally encompassing the first active region and defining a gate region in the second active region; forming the polysilicon layer in the second active region to a second polysilicon gate defined by the mask; implanting p-type impurities in source and drain regions defined in the second active region by the mask; diffusing the n-type impurities from the mask into source and drain regions defined in the first active region by the first polysilicon gate and into both the first and second polysilicon gates; and the combination of implantation and diffusion forming a self-aligned source and drain in each of the first and second active regions, and n-type doped first and second polysilicon gates.
Claim 4
Dependent Claim
203 words
A process for forming a CMOS integrated circuit from a structure comprising a body of n-type semiconductor material having a first and second active regions, respectively, with a p-well formed in the first active region, and a relatively thin silicon dioxide layer formed over said active regions, said process comprising: forming a first polysilicon gate over the silicon dioxide layer formed in said first active region and a polysilicon layer over the silicon dioxide layer in said second active region; forming a mask containing n-type impurities over the structure and laterally encompassing the first active region and defining a gate region in the second active region; forming the polysilicon layer in the second active region to a second polysilicon gate defined by the mask; implanting p-type impurities in source and drain regions defined in the second active region by the mask; diffusing the n-type impurities from the mask into source and drain regions defined in the first active region by the first polysilicon gate and into both the first and second polysilicon gates; and the combination of implantation and diffusion forming a self-aligned source and drain in each of the first and second active regions, and n-type doped first and second polysilicon gates.
Claim 5
Dependent Claim
49 words
The process as recited in claim 1 or 2 including, prior to said implantation step, the step of diffusing impurities from the mask into the source and drain regions defined in the first active region by the first polysilicon gate, and into both the first and second polysilicon gates.
Claim 6
Dependent Claim
14 words
The process as recited in claim 2 wherein the masking layer is arsenosilicate glass.
Claim 7
Dependent Claim
34 words
The process as recited in claim 4 further comprising forming prior to the diffusion step a relatively thin layer of silicon dioxide over the mask to prevent surface outgassing of impurities from the mask.
Claim 8
Dependent Claim
28 words
The process as recited in claim 2 wherein the thickness of the silicon dioxide layer is 300-1200 Angstroms and the thickness of the polysilicon layer is 3,000-8,000 Angstroms.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-23 | 1986-02-22 | 1986-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-23 | 1990-02-22 | 1990-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-23 | 1994-02-22 | 1994-08-24 | $7700.00 | Window Closed / Lapsed |