US4956689A
Expired / Lapsed
US
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High speed gallium arsenide transistor and method
Assignee: Texas Instruments Inc
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Filing: 1990-01-12
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Granted: 1990-09-11
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Expires: 2010-01-12
Abstract
Abstract Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced. This in turn reduces the capacitance associated with this junction and correspondingly improves device operating speed. By forming a portion of the collector in the trench, the lateral dimensions of the transistor may be reduced and higher levels of device integration are made possible.
Inventors
- 👤 Han-Tzong Yuan
- 👤 Liem Th. Tran
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:45
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/40; H10D10/461; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/85
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
113 words
A semiconductor integrated circuit including a bipolar transistor comprising a collector region, a base region and an emitter region forming a base to emitter junction, said base region comprising a doped region of a first layer of semiconductor material overlying said emitter region, the base to emitter junction of said transistor being defined by the bottom of a trench formed in at least a second layer of semiconductor material overlying the emitter region of said transistor, wherein electrical contact to said base region is accomplished by providing a region in said second layer along portions of the walls of said trench that is more highly doped than other portions of said second layer.
Claim 2
Dependent Claim
113 words
A semiconductor integrated circuit including a bipolar transistor comprising a collector region, a base region and an emitter region forming a base to emitter junction, said base region comprising a doped region of a first layer of semiconductor material overlying said emitter region, the base to emitter junction of said transistor being defined by the bottom of a trench formed in at least a second layer of semiconductor material overlying the emitter region of said transistor, wherein electrical contact to said base region is accomplished by providing a region in said second layer along portions of the walls of said trench that is more highly doped than other portions of said second layer.
Claim 3
Dependent Claim
21 words
The integrated circuit of claim 1, wherein said collector is formed in another layer of semiconductor material which overlies said trench.
Claim 4
Dependent Claim
27 words
The integrated circuit of claim 1, wherein said at least one layer of semiconductor material is a compound of elements from periodic table groups III and V.
Claim 5
Dependent Claim
25 words
The integrated circuit of claim 2, wherein said second layer of semiconductor material is a compound of elements from periodic table groups III and V.
Claim 6
Dependent Claim
12 words
The integrated circuit of claim 3, wherein said compound includes gallium arsenide.
Claim 7
Dependent Claim
12 words
The integrated circuit of claim 4, wherein said compound includes gallium arsenide.
Claim 8
Dependent Claim
192 words
A semiconductor integrated circuit comprising: a first layer of semiconductor material doped to a first conductivity type and including a bipolar emitter region; a second layer of undoped semiconductor material on said first layer having selectively doped regions of a second conductivity type formed therein to define a base region; a third layer of undoped semiconductor material on said second layer; a fourth layer of semiconductor material having at least surface portions doped to said second conductivity type at least partially on said second and third layers and including a bipolar base contact region; a fifth layer of semiconductor material doped to said first conductivity type and including a collector region which overlies a trench formed through said third and fourth layers and contacts at least portions of said selectively doped regions, wherein the sidewalls of said trench are doped to a first conductivity type to form a conductive path between said base region in said second layer and said base contact region in said fourth layer; and a plurality of conductors selectively disposed on said base contact region and said collector region to provide electrical contact terminals for a bipolar transistor.
Claim 9
Dependent Claim
192 words
A semiconductor integrated circuit comprising: a first layer of semiconductor material doped to a first conductivity type and including a bipolar emitter region; a second layer of undoped semiconductor material on said first layer having selectively doped regions of a second conductivity type formed therein to define a base region; a third layer of undoped semiconductor material on said second layer; a fourth layer of semiconductor material having at least surface portions doped to said second conductivity type at least partially on said second and third layers and including a bipolar base contact region; a fifth layer of semiconductor material doped to said first conductivity type and including a collector region which overlies a trench formed through said third and fourth layers and contacts at least portions of said selectively doped regions, wherein the sidewalls of said trench are doped to a first conductivity type to form a conductive path between said base region in said second layer and said base contact region in said fourth layer; and a plurality of conductors selectively disposed on said base contact region and said collector region to provide electrical contact terminals for a bipolar transistor.
Claim 10
Dependent Claim
25 words
An integrated circuit as recited in claim 7, wherein said layers of semiconductor material are compounds of elements from periodic table groups III and V.
Claim 11
Dependent Claim
14 words
An integrated circuit as recited in claim 8, wherein said compound is gallium arsenide.
Claim 12
Dependent Claim
18 words
An integrated circuit as recited in claim 7, wherein said first and third layers are aluminum gallium arsenide.
Claim 13
Dependent Claim
22 words
An integrated circuit as recited in claim 7, wherein said base region and the sidewalls of said trench are implanted with beryllium.
Claim 14
Dependent Claim
172 words
A bipolar transistor having reduced emitter to base junction area comprising: a semiconductor substrate doped to a first conductivity type and including a bipolar emitter region; a first layer of semiconductor material on said substrate including doped portions of a second conductivity type for providing an active base region and undoped portions for providing isolation regions; a second layer of undoped semiconductor material on said first layer; a third layer of semiconductor material doped to said second conductivity type on said second layer to form base contact regions, said active base region being formed at the bottom of an opening in said second and third layers of semiconductor material; a fourth layer of semiconductor material doped to said first conductivity type overlying at least a portion of said active base region to form a bipolar collector region; a first electrical contact formed on said collector region for providing a bipolar collector contact; and a second electrical conductor formed on at least one of said base contact regions for providing a base contact.
Claim 15
Dependent Claim
172 words
A bipolar transistor having reduced emitter to base junction area comprising: a semiconductor substrate doped to a first conductivity type and including a bipolar emitter region; a first layer of semiconductor material on said substrate including doped portions of a second conductivity type for providing an active base region and undoped portions for providing isolation regions; a second layer of undoped semiconductor material on said first layer; a third layer of semiconductor material doped to said second conductivity type on said second layer to form base contact regions, said active base region being formed at the bottom of an opening in said second and third layers of semiconductor material; a fourth layer of semiconductor material doped to said first conductivity type overlying at least a portion of said active base region to form a bipolar collector region; a first electrical contact formed on said collector region for providing a bipolar collector contact; and a second electrical conductor formed on at least one of said base contact regions for providing a base contact.
Claim 16
Dependent Claim
25 words
A bipolar transistor as recited in claim 12, wherein said layers of semiconductor material are compounds of elements from periodic table groups III and V.
Claim 17
Dependent Claim
14 words
A bipolar transistor as recited in claim 13, wherein said compound is gallium arsenide.
Claim 18
Dependent Claim
22 words
A bipolar transistor as recited in claim 12, wherein said substrate and said second layer of semiconductor material are aluminum gallium arsenide.
Claim 19
Dependent Claim
46 words
A bipolar transistor as recited in claim 12, wherein a conductive path between said active base region and said at least one of said base contact regions comprises a doped portion of said second and third layers of semiconductor material along a sidewall of said opening.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |