EP0206787A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Heterojunction bipolar transistor and method of manufacturing same
Assignee: Panasonic Holdings Corp
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Filing: 1986-06-20
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Granted: —
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Expires: 2006-06-20
Abstract
Abstract A heterojunction bipolar transistor having excellent high-frequency characteristics is manufactured by forming a semi-insulating semiconductor layer on a collector (or emitter) layer, removing a part of the semi-insulating semiconductor layer to form a cut portion so that the collector layer is exposed at the cut portion, growing a base layer on the semi-insulating semiconductor layer, on a slant wall of the cut portion and on the exposed part of the collector layer, and growing an emitter (or collector) layer on the base layer. A base layer may be preliminary formed on the semi-insulating semiconductor layer before forming the cut portion. Energy band gap of the emitter is greater than that of the base.
Inventors
- 👤 Kazuo Eda
- 👤 Masanori Inada
- 👤 Yorito Ota
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 07:49
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D62/85
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
148 words
A heterojunction bipolar transistor comprising: at least a collector (or emitter) layer (3) provided on a semiconductor substrate (1); a semi-insulating semiconductor layer (11) provided on said collector (or emitter) layer, said semi-insulating semiconductor layer having at least a cut portion where said semi-insulating semiconductor layer is partly removed so that said collector (or emitter) layer is partly exposed; a base layer (5) provided on the exposed portion of said collector (or emitter) layer; a first external base layer (4) provided on said semi-insulating semiconductor layer; a second external base layer (5) provided on a slant wall of said cut portion of said semi-insulating semiconductor layer for connecting said base layer and said first external base layer; and an emitter (or collector)layer (6) formed on said base layer, wherein energy band gap of said emitter (or collector) layer is greater than energy band gap of said base layer.
Claim 2
Dependent Claim
148 words
A heterojunction bipolar transistor comprising: at least a collector (or emitter) layer (3) provided on a semiconductor substrate (1); a semi-insulating semiconductor layer (11) provided on said collector (or emitter) layer, said semi-insulating semiconductor layer having at least a cut portion where said semi-insulating semiconductor layer is partly removed so that said collector (or emitter) layer is partly exposed; a base layer (5) provided on the exposed portion of said collector (or emitter) layer; a first external base layer (4) provided on said semi-insulating semiconductor layer; a second external base layer (5) provided on a slant wall of said cut portion of said semi-insulating semiconductor layer for connecting said base layer and said first external base layer; and an emitter (or collector)layer (6) formed on said base layer, wherein energy band gap of said emitter (or collector) layer is greater than energy band gap of said base layer.
Claim 3
Dependent Claim
18 words
The heterojunction bipolar transistor according to claim 1, wherein group III-V compound semiconductor is used for said layers.
Claim 4
Dependent Claim
41 words
The heterojunction bipolar transistor according to claim 1, wherein Al x Ga 1-x As (x> 0), GaAs and Al y Ga 1-y As (y > 0) are used for said emitter layer, said base layer and said semi-insulating semiconductor layer, respectively.
Claim 5
Dependent Claim
32 words
The heterojunction bipolar transistor according to claim 1, wherein said slant wall of said cut portion of said semi-insulating semiconductor layer has a portion which has a tilt angle less than 90°.
Claim 6
Dependent Claim
20 words
The heterojunction bipolar transistor according to claim 1, wherein said base layer is thinner than said first external base layer.
Claim 7
Independent Claim
191 words
A method of manufacturing a heterojunction bipolar transistor comprising the steps of: forming at least a collector (or emitter) layer (3) on a semiconductor substrate (1); forming a semi-insulating semiconductor layer (11) on said collector (or emitter) layer; removing at least a part of said semi-insulating semiconductor layer to form a cut portion so that said collector (or emitter) layer is partly exposed at said cut portion; epitaxially growing a base layer (4,5) on said semi-insulating semiconductor layer to be a first external base layer (4), on slant wall of said cut portion to be a second external base layer (5), and on the exposed portion of said collector (or emitter) layer to be a base; epitaxially growing an emitter (or collector) layer (6) on said base layer; and forming an emitter (or collector) electrode (10), a base electrode (9) and a collector (or emitter) electrode (8) on said emitter (or collector) layer at a portion in said cut portion, said first external base layer and said collector (or emitter) layer, respectively, wherein energy band gap of said emitter (or collector) layer is greater than energy band gap of said base.
Claim 8
Independent Claim
191 words
A method of manufacturing a heterojunction bipolar transistor comprising the steps of: forming at least a collector (or emitter) layer (3) on a semiconductor substrate (1); forming a semi-insulating semiconductor layer (11) on said collector (or emitter) layer; removing at least a part of said semi-insulating semiconductor layer to form a cut portion so that said collector (or emitter) layer is partly exposed at said cut portion; epitaxially growing a base layer (4,5) on said semi-insulating semiconductor layer to be a first external base layer (4), on slant wall of said cut portion to be a second external base layer (5), and on the exposed portion of said collector (or emitter) layer to be a base; epitaxially growing an emitter (or collector) layer (6) on said base layer; and forming an emitter (or collector) electrode (10), a base electrode (9) and a collector (or emitter) electrode (8) on said emitter (or collector) layer at a portion in said cut portion, said first external base layer and said collector (or emitter) layer, respectively, wherein energy band gap of said emitter (or collector) layer is greater than energy band gap of said base.
Claim 9
Dependent Claim
47 words
The method according to claim 6, wherein said first external base layer is preliminarily formed on said semi-insulating semiconductor layer before forming said cut portion, said cut portion being formed by removing at least a part of said first external base layer and said semi-insulating semiconductor layer.
Claim 10
Dependent Claim
40 words
The method according to claim 7, wherein GaAs and A1 Ga 1-y As (y ≧ 0) are used for said first external base layer and said semi-insulating semiconductor layer, respectively, and wherein said cut portion is formed by wet etching.
Claim 11
Dependent Claim
16 words
The method according to claim 7, wherein group III-V compound semiconductor is used for said layers.
Claim 12
Dependent Claim
38 words
The method according to claim 7, wherein A1 x Ga 1-x As (x > 0), GaAs and AlyGa 1-y As (y > 0) are used for said emitter layer, said base layer and said semi-insulating semiconductor layer, respectively.
Claim 13
Dependent Claim
36 words
The method according to claim 6, wherein Aly Ga 1- yAs (y > 0) is used for said semi-insulating semiconductor layer, and wherein said cut portion of said semi-insulating semiconductor layer is formed by wet etching.
References Cited (Backward Citations)
No citation records indexed.
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