Method for manufacture of semiconductor device

Claim 1

A method of manufacturing a transistor and at least one other device comprising the steps of forming N and P regions in a substrate, forming an insulating film (9) on the surface of said substrate, forming a resist mask (10) on said insulating film (9), selectively etching said insulating film (9) through said resist mask (10) to form a plurality of windows (9a, 9b, 9c) to said substrate, removing said resist mask (10), forming a polycrystalline layer (11) on said insulating film (9) and in said plurality of windows (9a, 9b, 9c), forming a resist mask (12) on said polycrystalline layer (11), ion-implanting a P-type impurity through a window (12R) of the resist mask (12) into a portion (11R) which will be a resistor of said polycrystalline layer (11), removing said resist mask (12), forming another resist mask (13) on said polycrystalline layer (11), ion-implanting through windows (13e 13b) of said resist mask (13) to form resistor contact portions (11e) and a base contact portion (11b) which will correspond to the base in said polycrystalline layer (11), removing said resist mask (13), forming another resist mask (14) on said polycrystalline layer (11), ion-implanting through windows (14e, 14c) of said resist mask (14) to form emitter and collector electrodes, removing said another resist mask (14), forming an insulating film (15) on said polycrystalline layer (11), heat treating said substrate structure and diffusing N-type from portion (11b) of said polycrystalline layer (11) which corresponds to the emitter region (16e) and from portion (11c) of polycrystalline layer (11) which corresponds to the collector contact into the base region (7) and the collector lead region 8 to form an emitter region (16e) and a collector contact (16c) and simultaneously diffusing the P-type impurity from portion (11b) which corresponds to the base contact of polycrystalline layer (11) into the base region (7) to form a base contact 16(b), removing said insulating film (15), forming patterns in said polycrystalline film (11) to leave the resistor part (11r), the resistor contact (11e) the portion (11e) which corresponds to the emitter region (16e), the portion (11b) which corresponds to the base contact (16b) and the portion (11c) which corresponds to the collector contact 916c) forming a thin film (17) on the surface of the semiconductor device forming a relatively thick insulating film (18) on said thinfilm (17), patterning said insulating film (18) so that is partially left on the resistor part (11r) and the resistor contact portion (11e), removing said thin film (17) except those portions under said insulating film (18), and forming resistor electrodes (19e) an emitter electrode (19c), a base electrode (19b) and a collector electrode (19c).

Claim 2

A method of manufacturing a transistor and at least one other device comprising the steps of forming N and P regions in a substrate, forming an insulating film (9) on the surface of said substrate, forming a resist mask (10) on said insulating film (9), selectively etching said insulating film (9) through said resist mask (10) to form a plurality of windows (9a, 9b, 9c) to said substrate, removing said resist mask (10), forming a polycrystalline layer (11) on said insulating film (9) and in said plurality of windows (9a, 9b, 9c), forming a resist mask (12) on said polycrystalline layer (11), ion-implanting a P-type impurity through a window (12R) of the resist mask (12) into a portion (11R) which will be a resistor of said polycrystalline layer (11), removing said resist mask (12), forming another resist mask (13) on said polycrystalline layer (11), ion-implanting through windows (13e 13b) of said resist mask (13) to form resistor contact portions (11e) and a base contact portion (11b) which will correspond to the base in said polycrystalline layer (11), removing said resist mask (13), forming another resist mask (14) on said polycrystalline layer (11), ion-implanting through windows (14e, 14c) of said resist mask (14) to form emitter and collector electrodes, removing said another resist mask (14), forming an insulating film (15) on said polycrystalline layer (11), heat treating said substrate structure and diffusing N-type from portion (11b) of said polycrystalline layer (11) which corresponds to the emitter region (16e) and from portion (11c) of polycrystalline layer (11) which corresponds to the collector contact into the base region (7) and the collector lead region 8 to form an emitter region (16e) and a collector contact (16c) and simultaneously diffusing the P-type impurity from portion (11b) which corresponds to the base contact of polycrystalline layer (11) into the base region (7) to form a base contact 16(b), removing said insulating film (15), forming patterns in said polycrystalline film (11) to leave the resistor part (11r), the resistor contact (11e) the portion (11e) which corresponds to the emitter region (16e), the portion (11b) which corresponds to the base contact (16b) and the portion (11c) which corresponds to the collector contact 916c) forming a thin film (17) on the surface of the semiconductor device forming a relatively thick insulating film (18) on said thinfilm (17), patterning said insulating film (18) so that is partially left on the resistor part (11r) and the resistor contact portion (11e), removing said thin film (17) except those portions under said insulating film (18), and forming resistor electrodes (19e) an emitter electrode (19c), a base electrode (19b) and a collector electrode (19c).

Claim 3

A method of manufacturing a transistor and at least two other devices comprising the steps of forming N and P regions on a substrate, forming an insulating film 9 on the surface of said substrate, forming a resist mask (10) on said insulating film (9), selectively etching said insulating film (9) through said resist mask (10) to form a plurality of windows (9a, 9b, 9c, 9g) to said substrate, removing said resist mask (10), forming a polycrystalline layer (11) on said insulating film (9) and in said plurality of windows (9e, 9b, 9c, 9b), forming a resist mask (12) on said polycrystalline layer (11), ion-implanting a P-type impurity through a window (12R) of the resist mask (12) into a portion (11R) which will be a resistor of said polycrystalline layer (11), removing said resist mask (12), forming another resist mask (13) on said polycrystalline layer (11), ion-implanting through windows (13f, 13b) of said resist mask (13) to form resistor contact portions (11t) and a base contact portion (11b) which will correspond to the base in said polycrystalline layer (11), removing said resist mask (13), forming another resist mask (14) on said polycrystalline layer (11), ion-implanting through windows (14e, 14c, 14g) of said resist mask (14) into a portion (11c) of polycrystalline layer (11) corresponding to the emitter region and the collector electrode and a portion (11g) of a lead of a capacitor, removing said another resist mask (14), patterning said polycrystalline layer (11) to leave resistor part (11r), resistor contact (11t), the emitter region, the base contact, the collector contact and one lead (11g) of the capacitor, forming a thin film (17) on said substrate structure, forming another insulating film on said thin film (17), heat treating said substrate structure and diffusing N-type from portion (11e) of said polycrystalline layer (11) which corresponds to the emitter region and from portion (11c) of polycrystalline layer (11) which corresponds to the collector contact, a portion (11g) corresponding to one capacitor lead into the base region (7) and the active region (6b) to form an emitter region (16e) and a collector contact (16c) and one lead of said capacitor and simultaneously diffusing the P-type ipurity from portion (11b) which corresponds to the base contact of polycrystalline layer (11) into the base region (7) to form a base contact 16(b), patterning said insulating film (15) to leave the resistor part (11r), the resistor contact (11f), patterning said thin film (17) so that the portion under insulating film (15) remains, forming another resist mask (20) on said substrate device, selectively etching said insulating film (9) to open a window (9m) which communicates with the active region (6b) and determines the capacitance of said capacitor, forming a film (21) on said substrate device, patterning said film (21) so that the portion of film (17) is left which corresponds to window (9m) and forming electrodes (19t) for said resistor (11r) an emitter electrode (19e), a base electrode (19g), a collector electrode (19c), a capacitor electrode (19g) and a capacitor electrode (19m).

Claim 4

A method of manufacturing a transistor and at least two other devices comprising the steps of forming N and P regions on a substrate, forming an insulating film 9 on the surface of said substrate, forming a resist mask (10) on said insulating film (9), selectively etching said insulating film (9) through said resist mask (10) to form a plurality of windows (9a, 9b, 9c, 9g) to said substrate, removing said resist mask (10), forming a polycrystalline layer (11) on said insulating film (9) and in said plurality of windows (9e, 9b, 9c, 9b), forming a resist mask (12) on said polycrystalline layer (11), ion-implanting a P-type impurity through a window (12R) of the resist mask (12) into a portion (11R) which will be a resistor of said polycrystalline layer (11), removing said resist mask (12), forming another resist mask (13) on said polycrystalline layer (11), ion-implanting through windows (13f, 13b) of said resist mask (13) to form resistor contact portions (11t) and a base contact portion (11b) which will correspond to the base in said polycrystalline layer (11), removing said resist mask (13), forming another resist mask (14) on said polycrystalline layer (11), ion-implanting through windows (14e, 14c, 14g) of said resist mask (14) into a portion (11c) of polycrystalline layer (11) corresponding to the emitter region and the collector electrode and a portion (11g) of a lead of a capacitor, removing said another resist mask (14), patterning said polycrystalline layer (11) to leave resistor part (11r), resistor contact (11t), the emitter region, the base contact, the collector contact and one lead (11g) of the capacitor, forming a thin film (17) on said substrate structure, forming another insulating film on said thin film (17), heat treating said substrate structure and diffusing N-type from portion (11e) of said polycrystalline layer (11) which corresponds to the emitter region and from portion (11c) of polycrystalline layer (11) which corresponds to the collector contact, a portion (11g) corresponding to one capacitor lead into the base region (7) and the active region (6b) to form an emitter region (16e) and a collector contact (16c) and one lead of said capacitor and simultaneously diffusing the P-type ipurity from portion (11b) which corresponds to the base contact of polycrystalline layer (11) into the base region (7) to form a base contact 16(b), patterning said insulating film (15) to leave the resistor part (11r), the resistor contact (11f), patterning said thin film (17) so that the portion under insulating film (15) remains, forming another resist mask (20) on said substrate device, selectively etching said insulating film (9) to open a window (9m) which communicates with the active region (6b) and determines the capacitance of said capacitor, forming a film (21) on said substrate device, patterning said film (21) so that the portion of film (17) is left which corresponds to window (9m) and forming electrodes (19t) for said resistor (11r) an emitter electrode (19e), a base electrode (19g), a collector electrode (19c), a capacitor electrode (19g) and a capacitor electrode (19m).