US4851838A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single chip successive approximation analog-to-digital converter with trimmable and controllable digital-to-analog converter
Assignee: Vermont Technical College
•
Filing: 1987-12-18
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Granted: 1989-07-25
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Expires: 2007-12-18
Abstract
Abstract A single chip monolithic integrated successive approximation analog-to-digital converter includes a test mode terminal for receiving shift register test mode control signals and successive approximation mode control signals. Digital test data signals are applied to a test data terminal. A trimmable digital-to-analog converter (DAC) is connected to receive digital signals and converts these signals to analog signals of corresponding values. A successive approximation and shift register is coupled to the test mode terminal and the test data terminal. During post-fabrication processing, the successive approximation and shift register operates in a shift register test mode in response to the test mode control signals. Test signals of a known value are serially received and applied in parallel to the DAC. The DAC can then be trimmed to required specifications. The successive approximation and shift register operates in a successive approximation mode in response to successive approximation mode control signals.
Inventors
- 👤 John S. Shier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 02:38
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1071; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/46; H03M1/66; H03M1/74
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
121 words
A single chip integrated successive approximation analog-to-digital converter, including: test mode terminal means for receiving test mode control signals and successive approximation mode control signals; test data terminal means for receiving digital test data signals; a trimmable digital-to-analog converter (DAC) having input terminals for receiving digital signals and for converting the digital signals to analog signals of corresponding values; and successive approximation register means coupled to the test mode terminal means and test data terminal means for operating in a test mode and applying the test data signals to the input terminals of the DAC in response to the test mode control signals, and for operating in a successive approximation register mode in response to the successive approximation mode control signals.
Claim 2
Dependent Claim
121 words
A single chip integrated successive approximation analog-to-digital converter, including: test mode terminal means for receiving test mode control signals and successive approximation mode control signals; test data terminal means for receiving digital test data signals; a trimmable digital-to-analog converter (DAC) having input terminals for receiving digital signals and for converting the digital signals to analog signals of corresponding values; and successive approximation register means coupled to the test mode terminal means and test data terminal means for operating in a test mode and applying the test data signals to the input terminals of the DAC in response to the test mode control signals, and for operating in a successive approximation register mode in response to the successive approximation mode control signals.
Claim 3
Dependent Claim
51 words
The analog-to-digital converter of claim 1 wherein: the test data terminal means serially receives the digital test data signals; and the successive approximation register means comprises successive approximation and shift register means for serially receiving the test data signals and for providing the test data signals to the DAC in parallel.
Claim 4
Dependent Claim
40 words
The analog-to-digital converter of claim 2 and further including: an input terminal for receiving analog input signals; a comparator coupled to the input terminal and the DAC; and a latch coupled between the comparator and the successive approximation register means.
Claim 5
Dependent Claim
17 words
The analog-to-digital converter of claim 3 wherein the successive approximation and shift register means includes bipolar transistors.
Claim 6
Dependent Claim
20 words
The analog-to-digital converter of claim 3 wherein the successive approximation and shift register means is implemented with current mode logic.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |