US4451820A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Charge redistribution integratable D/A convertor
Assignee: AG Communication Systems Corp
•
Filing: 1981-08-27
•
Granted: 1984-05-29
•
Expires: 2001-08-27
Abstract
Abstract A D/A converter having a feedback capacitor C1 between the inverting input and output of an operational amplifier A1 having a virtual ground on the inverting input. First switch means is sequentially responsive to binary values of bits of a digital input word for connecting a bus line to either a reference voltage or ground. Second switch means alternately connects opposite sides of a second capacitor C2=C1 between ground and the bus line for sampling the logic level of a bit, and across C1 for redistributing sampled charge during each bit. The charge on C1 is transferred to a storage capacitor and then reset to zero at the end of each word. In an alternate embodiment, one of a pair of switched capacitors samples the logic level while the other is connected across C1 for redistributing stored charge. In another embodiment, binary weighted capacitors sample the logic levels of bits in pairs and are simultaneously connected across C1 for redistributing charge. In another embodiment, n switched capacitors simultaneously sample the logic levels of associated bits and are sequentially connected across A1 for redistributing charge.
Inventors
- 👤 Christopher W. Kapral
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 12:19
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/72
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
201 words
An integratable digital to analog converter comprising: first and second capacitors having capacitances of the same values, and having one and other sides thereof; a differential input operational amplifier means having an inverting input terminal and an output terminal electrically connected to one and other sides, respectively, of said first capacitor and having a non-inverting input electrically connected to ground for impressing a virtual ground potential on said inverting input terminal; first switch means sequentially responsive to each binary bit in a digital input word for impressing onto a first bus line one of a prescribed voltage from a voltage source and the ground reference voltage which may correspond to a binary one and zero in the associated bit position; and second switch means operative for each bit cycle of the digital input word in said first switch means for first connecting said one and other sides of said second capacitor to ground and said bus line, respectively, for sampling the bus voltage, and then connecting said one and other sides of said second capacitor to associated sides of said first capacitor for redistributing the sampled charge-voltage on said second capacitor and any charge-voltage on said first capacitor between these capacitors.
Claim 2
Dependent Claim
201 words
An integratable digital to analog converter comprising: first and second capacitors having capacitances of the same values, and having one and other sides thereof; a differential input operational amplifier means having an inverting input terminal and an output terminal electrically connected to one and other sides, respectively, of said first capacitor and having a non-inverting input electrically connected to ground for impressing a virtual ground potential on said inverting input terminal; first switch means sequentially responsive to each binary bit in a digital input word for impressing onto a first bus line one of a prescribed voltage from a voltage source and the ground reference voltage which may correspond to a binary one and zero in the associated bit position; and second switch means operative for each bit cycle of the digital input word in said first switch means for first connecting said one and other sides of said second capacitor to ground and said bus line, respectively, for sampling the bus voltage, and then connecting said one and other sides of said second capacitor to associated sides of said first capacitor for redistributing the sampled charge-voltage on said second capacitor and any charge-voltage on said first capacitor between these capacitors.
Claim 3
Dependent Claim
28 words
The converter according to claim 1 wherein said first switch means is sequentially responsive to bits in ascending order of the bit position in the digital input word.
Claim 4
Dependent Claim
28 words
The converter according to claim 2 wherein said first and second capacitors are integrated capacitors and their one and other sides and the top and bottom plates thereof.
Claim 5
Dependent Claim
55 words
The converter according to claim 3 comprising third switch means operative subsequent to redistribution of the charge on said second capacitor that is associated with the most significant bit in the digital input word for resetting the charge voltage on said first capacitor to substantially zero volts prior to receipt of the next digital word.
Claim 6
Dependent Claim
65 words
The converter according to claim 4 further comprising sample-hold means periodically operative for sampling and holding the output voltage of said amplifier for a charge voltage on said first capacitor obtained from a redistribution of the charge on said second capacitor for the most significant bit in the digital input word prior to said third switch means resetting the charge voltage on said first capacitor.
Claim 7
Independent Claim
211 words
The method of converting a digital input word, corresponding to a binary number, to an associated analog signal comprising the steps of: electrically connecting one and other sides of a first capacitor to the inverting input terminal and the output terminal of a differential input operational amplifier means; electrically connecting the non-inverting input of the amplifier to a ground reference voltage for impressing a virtual ground potential on its inverting input terminal; the amplifier and first capacitor, which is a feedback capacitor, operating as a voltage source; sequentially impressing one of a prescribed voltage from a voltage source and the ground reference voltage on a bus line for a binary one and zero, respectively, in the associated bit position in the digital word; and electrically connecting one and other sides of a second capacitor, having a capacitance equal to that of the first capacitor, to ground and the bus line for sampling the bus voltage, and then electrically connecting the one and other sides of the second capacitor to associated sides of the first capacitor for redistributing the sampled charge-voltage on the second capacitor and any charge-voltage on the first capacitor between these capacitors during each bit cycle of the digital input word and associated voltage impressed on the bus line.
Claim 8
Independent Claim
211 words
The method of converting a digital input word, corresponding to a binary number, to an associated analog signal comprising the steps of: electrically connecting one and other sides of a first capacitor to the inverting input terminal and the output terminal of a differential input operational amplifier means; electrically connecting the non-inverting input of the amplifier to a ground reference voltage for impressing a virtual ground potential on its inverting input terminal; the amplifier and first capacitor, which is a feedback capacitor, operating as a voltage source; sequentially impressing one of a prescribed voltage from a voltage source and the ground reference voltage on a bus line for a binary one and zero, respectively, in the associated bit position in the digital word; and electrically connecting one and other sides of a second capacitor, having a capacitance equal to that of the first capacitor, to ground and the bus line for sampling the bus voltage, and then electrically connecting the one and other sides of the second capacitor to associated sides of the first capacitor for redistributing the sampled charge-voltage on the second capacitor and any charge-voltage on the first capacitor between these capacitors during each bit cycle of the digital input word and associated voltage impressed on the bus line.
Claim 9
Dependent Claim
33 words
The method according to claim 6 wherein voltages are sequentially impressed on the bus line for each binary bit in the digital input word in the ascending order of the bit position thereof.
References Cited (Backward Citations)
US3541446A
Cited
US3987435A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-05-29 | 1987-11-28 | 1988-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-05-29 | 1991-11-28 | 1992-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-05-29 | 1995-11-28 | 1996-05-29 | $7700.00 | Window Closed / Lapsed |