US3987435A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog-to-digital converter utilizing time reference for effecting conversion
Assignee: Suwa Seikosha KK
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Filing: 1974-11-27
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Granted: 1976-10-19
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Expires: 1994-11-27
Abstract
Abstract An analog-to-digital converter adapted to utilize a counting circuit including a quartz crystal vibrator time standard as the time reference for effecting analog-to-digital conversion. The converter includes oscillator means for producing a time standard signal, and counter means including a plurality of series-connected divider stages adapted to produce timing signals representative of the counts thereof in response to the time standard signal. Coincidence circuitry is coupled to a first plurality of the divider stages to produce a signal in response to the coincidence of the count of the first plurality of counters and a preselected count of the coincidence circuit. Control means produce first and second control signals in response to the coincidence signal from the coincidence circuit and the timing signals from the remaining divider stages in the counter circuit. Voltage supply circuitry is coupled to the control circuitry in order to apply an analog voltage in response to a first control signal, and in response to a second control signal from said control means, apply a reference voltage of a polarity opposite to the analog voltage to integrate the analog voltage applied thereto, and thereby effect an integration of the reference voltage of opposite polarity applied thereto, to thereby sum both voltages to zero. Digital processing circuitry is coupled to said integrator circuit and the first plurality of divider stages, and in response to detecting the integrator circuit summing to zero, processes to elapsed time required for the reference voltage to be summed to zero counted by the first plurality of divider stages, the elapsed time digitally representing the analog voltage applied to the integrator circuit.
Inventors
- 👤 Masayuki Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:21
CPC Classifications
G; G06; G06J; G06J1/00; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
322 words
In an analog-to-digital converter having oscillator means for producing a time standard signal, and counter means incuding a plurality of series connected divider stage means adapted to produce timing signals representative of the count thereof in response to said time standard signal, the improvement comprising: coincidence means coupled to a first plurality of said divider stage means for producing a coincidence signal in response to the coincidence in the count of the first plurality of divider stages and a preselected count of said coincidence means; control means for seriatim producing first and second control signals in response to the timing signals produced by the remaining divider stage means in said counter means, said control means also producing a third control signal in response to said coincidence signal being applied thereto; voltage supply means coupled to said control means for respectively producing one of an analog voltage in response to said first control signal being applied thereto and a reference voltage of a polarity opposite to said analog voltage in response to said second control signal being applied thereto, said voltage supply means in response to said third control signal being applied thereto terminating the producing of said analog signal; integrator means coupled to said voltage supply means for seriatim integrating said analog voltage and said reference voltage of opposite polarity produced by said voltage supply means to thereby sum both voltages received thereby and in response to summing said voltages to zero producing a data transfer signal; and digital processing means coupled to said first plurality of divider stage means, and in response to said data transfer signal being applied thereto processing the elapsed time counted by the first plurality of divider stage means, the elapsed time digitally representing the analog voltage applied to the integrator circuit whereby the elapsed time over which the voltage is converted is selectable to be N times larger than the frequency of any superposed noise voltage.
Claim 2
Dependent Claim
322 words
In an analog-to-digital converter having oscillator means for producing a time standard signal, and counter means incuding a plurality of series connected divider stage means adapted to produce timing signals representative of the count thereof in response to said time standard signal, the improvement comprising: coincidence means coupled to a first plurality of said divider stage means for producing a coincidence signal in response to the coincidence in the count of the first plurality of divider stages and a preselected count of said coincidence means; control means for seriatim producing first and second control signals in response to the timing signals produced by the remaining divider stage means in said counter means, said control means also producing a third control signal in response to said coincidence signal being applied thereto; voltage supply means coupled to said control means for respectively producing one of an analog voltage in response to said first control signal being applied thereto and a reference voltage of a polarity opposite to said analog voltage in response to said second control signal being applied thereto, said voltage supply means in response to said third control signal being applied thereto terminating the producing of said analog signal; integrator means coupled to said voltage supply means for seriatim integrating said analog voltage and said reference voltage of opposite polarity produced by said voltage supply means to thereby sum both voltages received thereby and in response to summing said voltages to zero producing a data transfer signal; and digital processing means coupled to said first plurality of divider stage means, and in response to said data transfer signal being applied thereto processing the elapsed time counted by the first plurality of divider stage means, the elapsed time digitally representing the analog voltage applied to the integrator circuit whereby the elapsed time over which the voltage is converted is selectable to be N times larger than the frequency of any superposed noise voltage.
Claim 3
Dependent Claim
59 words
An analog-to-digital converter as claimed in claim 1 wherein said control means in response to said coincidence signal applies said second signal to said voltage supply means to effect an application of said reference voltage of a polarity opposite to the analog voltage to the integrator circuit, and resets the count of the first plurality of divider stage means.
Claim 4
Dependent Claim
74 words
An analog-to-digital converter as claimed in claim 1 wherein said coincidence means includes digital value setting means for determining a time reference over which said analog voltage is integrated by setting same to a preselected count, and a coincident detector for sensing the coincidence between the time counted by the first plurality of divider stage means and the digital value setting means, and in response thereto applying a coincidence signal to said control means.
Claim 5
Dependent Claim
58 words
An analog-to-digital converter as claimed in claim 3 wherein said control means in response to the coincident application of said second control signal and said coincidence signal effects an application of said reference voltage of a polarity opposite to the analog voltage to the integrator circuit, and resets the count of the first plurality of divider stage means.
Claim 6
Dependent Claim
89 words
An analog-to-digital converter as claimed in claim 3, wherein said voltage supply means includes at least three switch means coupled to said control means, said first switch means being actuated by said first control signal produced by said control means to effect application of said analog voltage to the integrator means, one of said second and third switches being actuated by said second control signal produced by said control means to effect application of said reference voltage of a polarity opposite to the analog voltage to said integrator means.
Claim 7
Dependent Claim
40 words
An analog-to-digital converter as claimed in claim 5, wherein said integrator means includes a reset means coupled to said control means to effect resetting of said integrator means in response to said first control signal produced by said control means.
Claim 8
Dependent Claim
50 words
An analog-to-digital converter as claimed in claim 3, wherein said digital processing means includes memory means for storing the time counted by the first plurality of divider stage means required for the reference voltage to effect summing of the integrator circuit to zero, in response to said data transfer signal.
Claim 9
Dependent Claim
102 words
An analog-to-digital converter as claimed in claim 7, wherein said integrator means includes an integrator circuit coupled to said voltage supply means, a comparator coupled to said integrator circuit for comparing signals integrated thereby, said comparator in response to a summing to zero supplying a signal representative thereof, a flip-flop adapted to receive said comparison signal as a first input, and said time standard signal as a second input, and in response to said time standard signal and comparator signal, produce a flip-flop pulse, and differentiator means adapted to receive said flip-flop pulse and in response thereto produce said data transfer signal.
Claim 10
Dependent Claim
24 words
An analog-to-digital converter as claimed in claim 3, wherein the preselected count of said digital value setting means is adapted to be remotely set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-19 | 1980-04-19 | 1980-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-19 | 1984-04-19 | 1984-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-19 | 1988-04-19 | 1988-10-19 | $7700.00 | Window Closed / Lapsed |