Asynchronously controllable successive approximation analog-to-digital converter

Claim 2

An analog-to-digital converter of the successive approximation type, comprising: a successive approximation register for holding successive trial solutions to an analog-to-digital conversion; means for comparing an analog input signal with the analog equivalent of the contents of the successive approximation register; control means for directing operations on said successive approximation register, as regulated by periodic clock signals and less frequent start-convert signals synchronized with the clock signals; means for generating the synchronized start-convert signals from asynchronous start-convert signals not having any definite timing relationship to the clock signals; and wherein said means for generating the synchronized start-convert signals includes first storage means including a first pair of flip-flops switchable to a selected storage state in response to the occurrence of an asynchronous start-convert signal for registering the occurrence of an asynchronous start-convert signal, and second storage means coupled to said first storage means for generating a synchronous start-convert signal upon the occurrence of a clock signal after said first storage means has registered the occurrence of an asynchronous start-convert signal.

Claim 3

An analog-to-digital converter as set forth in claim 2, wherein: said second storage means includes a plurality of additional flip-flops coupled in a sequential chain to one of said first pair of flip-flops, in such a manner that each level change in the clock signal propagates the selected storage state into one more of said flip-flops in the sequential chain; and the last of said flip-flops in the chain provides an output signal synchronized with the clock signals.

Claim 4

An analog-to-digital converter as set forth in claim 2, wherein the synchronized output signal is also fed back as a reset signal, to reset said first pair of flip-flops, which results in resetting each of said flip-flops in the sequential chain in turn, from the selected storage state, and also precludes the detection of a subsequent asynchronous start-convert signal until the reset signal is terminated.

Claim 5

An analog-to-digital converter as set forth in claim 3, wherein: said first pair of flip-flops include a first flip-flop that is set to the selected storage state upon the simultaneous presence of the asynchronous start-convert signal and a continuous-convert signal, and a second flip-flop that is set to the same state as the first flip-flop in the presence of the asynchronous start-convert signal; and the reset signal that is applied to said first pair of flip-flops is not terminated until conversion is complete, at which time said first and second flip-flops are successively set again to initiate a subsequent conversion automatically.

Claim 6

An analog-to-digital converter of the successive approximation type, comprising: a successive approximation register for holding successive trial solutions to an analog-to-digital conversion; means for comparing an analog input signal with the analog equivalent of the contents of the successive approximation register; control means for directing operations on said successive approximation register, as regulated by periodic clock signals and less frequent start-convert signals synchronized with the clock signals; means for generating the synchronized start-convert signals from asynchronous start-convert signals not having any definite timing relationship to the clock signals; and wherein said means for generating the synchronized start-convert signals includes first storage means including resetting means for connecting the synchronous start-convert signal to reset said first storage means and hold said first storage means in the reset condition until completion of a conversion process for registering the occurrence of a start convert signal, and second storage means coupled to said first storage means for generating a synchronous start-convert signal upon the occurrence of a clock signal after said first storage means has registered the occurrence of a start convert signal.

Claim 7

An analog-to-digital converter of the successive approximation type, comprising: a successive approximation register for holding successive trial solutions to an analog-to-digital conversion; means for comparing an analog input signal with the analog equivalent of the contents of the successive approximation register; control means for directing operations on said successive approximation register, as regulated by periodic clock signals and less frequent start-convert signals synchronized with the clock signals; means for generating the synchronized start-convert signals from asynchronous start-convert signals not having any definite timing relationship to the clock signals; and wherein said means for generating the synchronized start-convert signals includes first storage means including resetting means for connecting the synchronous start-convert signal to reset said first storage means and hold said first storage means in the reset condition until completion of a conversion process for registering the occurrence of a start convert signal, and second storage means coupled to said first storage means for generating a synchronous start-convert signal upon the occurrence of a clock signal after said first storage means has registered the occurrence of a start convert signal.

Claim 8

An analog-to-digital converter as set forth in claim 5, and further including circuit means for setting said first pair of flip-flops to the selected state upon the continuous presence of a start-convert signal and a continuous-convert signal, said first storage means being reset only by said resetting means; whereby a new synchronous converter control signal is generated automatically after a conversion is completed, provided the start-convert and continuous-convert signals are continuously present.

Claim 9

An analog-to-digital converter of the successive approximation type, comprising: a successive approximation register for holding successive trial solutions to an analog-to-digital conversion; means for comparing an analog input signal with the analog equivalent of the contents of the successive approximation register; control means for directing operations on said successive approximation register, as regulated by periodic clock signals and less frequent converter control signals synchronized with the clock signal; means for generating the synchronized converter control signals from asynchronous converter control signals not having any definite timing relationship to the clock signals; and wherein said means for generating the synchronized converter control signals includes first storage means including a first pair of flip-flops switchable to a selected storage state in response to the occurrence of an asynchronous converter control signal for registering the occurrence of an asynchronous converter control signal, and second storage means coupled to said first storage means, for generating a synchronous converter control signal upon the occurrence of a clock signal after said first storage means has registered the occurrence of an asynchronous converter control signal.

Claim 10

An analog-to-digital converter of the successive approximation type, comprising: a successive approximation register for holding successive trial solutions to an analog-to-digital conversion; means for comparing an analog input signal with the analog equivalent of the contents of the successive approximation register; control means for directing operations on said successive approximation register, as regulated by periodic clock signals and less frequent converter control signals synchronized with the clock signal; means for generating the synchronized converter control signals from asynchronous converter control signals not having any definite timing relationship to the clock signals; and wherein said means for generating the synchronized converter control signals includes first storage means including a first pair of flip-flops switchable to a selected storage state in response to the occurrence of an asynchronous converter control signal for registering the occurrence of an asynchronous converter control signal, and second storage means coupled to said first storage means, for generating a synchronous converter control signal upon the occurrence of a clock signal after said first storage means has registered the occurrence of an asynchronous converter control signal.

Claim 11

An analog-to-digital converter as set forth in claim 7, wherein: said second storage means includes a plurality of additional flip-flops coupled in a sequential chain to one of said first pair of flip-flops, in such a manner that each level change in the clock signal propagates the selected storage state into one more of said flip-flops in the sequential chain; and the last of said flip-flops in the chain provides an output signal synchronized with the clock signals.

Claim 12

An analog-to-digital converter as set forth in claim 8, wherein the synchronized output signal is also fed back as a reset signal, to reset said first pair of flip-flops, which results in resetting each of said flip-flops in the sequential chain in turn, from the selected storage state, and also precludes the detection of a subsequent asynchronous converter control signal until the reset signal is terminated.