US4441198A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shift register circuit
Assignee: Panasonic Holdings Corp
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Filing: 1981-06-22
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Granted: 1984-04-03
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Expires: 2001-06-22
Abstract
Abstract A first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.
Inventors
- 👤 Jun Shibata
- 👤 Haruyasu Yamada
- 👤 Toshiki Mori
- 👤 Toyoki Takemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:32
CPC Classifications
G; G11; G11C; G11C19/00; H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
168 words
A shift register circuit comprising: means for supplying a pair of clock pulse signals having different phases; a first flip-flop having an input and an output; a second flip-flop having first and second inputs and first and second outputs which are 180° out-of-phase, one of said outputs being directly connected to the input of said first flip-flop; a third flip-flop having first and second inputs and first and second outputs which are 180° out-of-phase, one of said outputs being directly connected to the first input of said second flip-flop; a first gate coupling the output of said first flip-flop to the second input of said second flip-flop; a second gate coupling the other of the outputs of said second flip-flop to one of the inputs of said third flip-flop; said first and second gates being suitably controlled on and off by the different phases of said clock pulse signals; and said first flip-flop being set and said second and said third flip-flops being reset by a reset signal.
Claim 2
Dependent Claim
168 words
A shift register circuit comprising: means for supplying a pair of clock pulse signals having different phases; a first flip-flop having an input and an output; a second flip-flop having first and second inputs and first and second outputs which are 180° out-of-phase, one of said outputs being directly connected to the input of said first flip-flop; a third flip-flop having first and second inputs and first and second outputs which are 180° out-of-phase, one of said outputs being directly connected to the first input of said second flip-flop; a first gate coupling the output of said first flip-flop to the second input of said second flip-flop; a second gate coupling the other of the outputs of said second flip-flop to one of the inputs of said third flip-flop; said first and second gates being suitably controlled on and off by the different phases of said clock pulse signals; and said first flip-flop being set and said second and said third flip-flops being reset by a reset signal.
Claim 3
Dependent Claim
34 words
A shift register circuit according to claim 1 further comprising latch circuits one for each of said flip-flops, said latch circuits being driven by at least one of the outputs of the respective flip-flops.
Claim 4
Dependent Claim
70 words
A shift register circuit according to claim 1 wherein said latch circuits each comprises a write gate circuit which determines a write state of an external signal in response to the output of a respective flip-flop and a flip-flop circuit for holding the write state of said write gate circuit, the write gate circuits and said first and second gates being driven by the clock pulse signals of different phases.
Claim 5
Dependent Claim
57 words
A shift register circuit according to claim 3 wherein each said write gate circuit writes an external signal in response to a clock pulse signal of different phase from a clock pulse signal applied to the coupling gate of the associated flip-flop and the output of the flip-flop which is next in sequence to the associated flip-flop.
Claim 6
Dependent Claim
56 words
A shift register circuit according to claim 3 wherein each said write gate circuit writes an external signal in response to an output of a flip-flop which is next in sequence to a flip-flop associated with said write gate circuit and an output of a flip-flop which is next in sequence to said sequentially next flip-flop.
Claim 7
Dependent Claim
17 words
A logic circuit according to claim 3 wherein said write gate circuits are driven by external pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-04-03 | 1987-10-03 | 1988-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-04-03 | 1991-10-03 | 1992-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-04-03 | 1995-10-03 | 1996-04-03 | $7700.00 | Window Closed / Lapsed |