Logic network with a low-power shift register

Claim 2

An integrated logic circuit comprising: at least first and second interconnected stages coupled to a source of potential, each stage including a binary memory cell, switchable between a saturated conductive state, representative of a first binary value and a nonconductive cutoff state, wherein no electrical energy is consumed, representative of a second binary value; a clockable gating means including a first gate coupled between the output of the first stage and the input of the second stage so that when the cell of the first stage is in the saturated conductive state and a clock pulse is applied to the first gate, the cell of the second stage is switched to the saturated conductive state; a second gate coupled between the input of the first stage and the output of the second stage so that when the cell of the second stage is in the saturated conductive state and a clock pulse is applied to the second gate, the cell of the first stage is switched to the nonconductive cutoff state; and means for presetting the cell of at least one stage to the conductive state and the cell of the other stage to the nonconductive state.

Claim 3

The arrangement as recited in claim 1 wherein said circuit includes n stages, n being greater than two, the stages being arranged in a sequence, with the gating means of each stage comprising first and second gates, coupled between the cell of their respective stage and the cell of an adjacent stage, said first and second gates being responsive to clock signals for switching the cell of the adjacent cell to its saturated conductive state and for resetting the cell of their respective stage to its nonconductive state if the cell of their respective stage prior to the application of the clock signals was in said saturated conductive state, said presetting means being coupled to said n stages to set at least one cell in its saturated conductive state with cells of the adjacent stages being preset to their nonconductive state.

Claim 4

The arrangement as recited in claim 2 wherein in the gating means of each stage said first gate has at least first and second input terminals and at least one output terminal, said coupling means including means coupling said first input terminal to the cell of the gate''s respective stage and coupling said second input terminal to a clock line and further coupling the output terminal of said first gate to the cell of an adjacent stage, whereby upon the application of a clock pulse on said clock line, said first gate provides a signal at its output terminal switching the cell of the adjacent stage to its saturated conductive state if the cell of the gate''s respective stage is in said saturated conductive state, said second gate having at least one input terminal and an output terminal and said means for coupling couple the input terminal of said second gate to the cell of the adjacent stage and the output terminal to the cell of the gate''s respective stage for switching the latter cell to its nonconductive state when the cell of the adjacent cell is driven by said first gate to its saturated conductive state.

Claim 5

The arrangement as recited in claim 3 wherein each of said first and second gates comprises a single transistor having a base, an emitter and a collector, the base and emitter defining input terminals and the collector defining the output terminal.

Claim 6

The arrangement as recited in claim 4 wherein in each stage said first gate includes a third input terminal and a second output terminal, the second output terminal being connected to the third input terminal of the first gate of the succeeding stage to inhibit the switching of only the cell of the succeeding stage to the saturated conductive state.

Claim 7

The arrangement as recited in claim 4 wherein said first gate comprises first and seCond transistors, with the bases of the two transistors defining two of the first gate''s input terminals, the emitters of the two transistors being connected to define the third input terminal of said first gate and the collectors of the two transistors defining the first gate''s first and second output terminals.

Claim 8

A low power shift register comprising: n identical stages coupled to a source of potential, and arranged in a sequence, each stage including a binary memory cell switchable between a saturated conductive state, representative of a first binary value, and a nonconductive cutoff state wherein no electrical power is consumed, representative of a second binary value, and, clockable gating means comprising: a first gate coupled between the output of the cell of its respective stage and the input of the cell of the next succeeding stage so that when the cell of the respective stage is in the saturated conductive state and clock pulse is applied to the first gate the cell of the next stage is switched to the saturated conductive state; and, a second gate coupled between the input of its respective stage and the output of the next stage so that when the cell of the next stage is in the saturated conductive state and a clock pulse is applied to the second gate, the cell of the respective stage is switched to the nonconductive cutoff state; means for presetting the cells of said n stages so that at least one selected cell is in its saturated conductive state, with the cells of stages adjacent said one cell to their nonconductive cutoff state.

Claim 9

A low power shift register comprising: n identical stages coupled to a source of potential, and arranged in a sequence, each stage including a binary memory cell switchable between a saturated conductive state, representative of a first binary value, and a nonconductive cutoff state wherein no electrical power is consumed, representative of a second binary value, and, clockable gating means comprising: a first gate coupled between the output of the cell of its respective stage and the input of the cell of the next succeeding stage so that when the cell of the respective stage is in the saturated conductive state and clock pulse is applied to the first gate the cell of the next stage is switched to the saturated conductive state; and, a second gate coupled between the input of its respective stage and the output of the next stage so that when the cell of the next stage is in the saturated conductive state and a clock pulse is applied to the second gate, the cell of the respective stage is switched to the nonconductive cutoff state; means for presetting the cells of said n stages so that at least one selected cell is in its saturated conductive state, with the cells of stages adjacent said one cell to their nonconductive cutoff state.

Claim 10

The arrangement as recited in claim 7 wherein each cell includes a pair of interconnected transistors of opposite conductivity type and said clockable gating means include a pair of gates comprising a first clockable gate coupled to the two transistors of the cell of its respective stage and to the two transistors of the cell of the adjacent stage, for responding to a clock pulse to switch the two transistors of the cell of the adjacent stage to their saturated conductive state if the two transistors of the cell of its respective stage are in their saturated conductive state, said clockable gating means further including a second gate coupled to one of the transistors of the cell of the adjacent stage and to the two transistors of the cell of its respective stage for switching the latter transistors to their cutoff state if the transistors of the cell of the adjacent stage are in the saturated conductive state, whereby in the absence of a clock pulse only the transistors of at least one cell are in their saturated conductive state and the transistors of cells in preceding and succeeding stages in said sequence are in their nonconductive states.

Claim 11

The arrangement as recited in claim 8 further including a diode matrix coupled to the cells of the second through the nth stages, for providing an indication in binary from of the cell of said stages to which it is connected which is in said saturated conductive state.

Claim 12

The arrangement as recited in claim 8 wherein the clockable gating means of each stage include a first pair of gates coupled between the stage''s cell and the cell of a succeeding stage viewed from left to right for shifting in response to a right shifting clock pulse, the saturated conductive state of the transistors of the cell of its respective cell to the transistors of the cell of the succeeding stage and for driving the transistors of the cell of its respective stage to their cutoff state and a second pair of gates coupled between the stages cell and a preceding cell for shifting in response to a left shifting clock pulse the saturated conductive state of the transistors of the stage''s cell to the transistors of the cell of the preceding stage and for driving the transistors of the cell of its respective stage to their cutoff state.

Claim 13

The arrangement as recited in claim 10 further including a diode matrix coupled to the cells of the second thrOugh the nth stages, for providing an indication in binary form of the cell of said stages to which it is connected which is in said saturated conductive state.

Claim 14

A low-power shift register comprising: n stages each including first and second transistors of opposite conductivity types interconnected to form a binary memory cell for storing a first binary value when said first and second transistors are in a saturated conductive state and for storing a second binary value when said first and second transistors are in a nonconductive cutoff state wherein no electrical energy is consumed, and at least one pair of clockable transistors including third and fourth transistors; and means including coupling means for coupling said stages to a source of potential and for interconnecting said stages to form a sequence of stages, with the third transistor of each stage coupled to the output of its stage and to a setting input of a succeeding stage to set the first and second transistors of the succeeding stage to their saturated state when a clock pulse is applied to said third transistor if the first and second transistors of its stage are in their saturated state, and the fourth transistor of each stage being coupled to a resetting input of its stage and to an output of the succeeding stage for resetting the first and second transistors of its stage to their nonconductive cutoff state if the first and second transistors of the succeeding stage are set to their saturated conductive state.

Claim 15

A low-power shift register comprising: n stages each including first and second transistors of opposite conductivity types interconnected to form a binary memory cell for storing a first binary value when said first and second transistors are in a saturated conductive state and for storing a second binary value when said first and second transistors are in a nonconductive cutoff state wherein no electrical energy is consumed, and at least one pair of clockable transistors including third and fourth transistors; and means including coupling means for coupling said stages to a source of potential and for interconnecting said stages to form a sequence of stages, with the third transistor of each stage coupled to the output of its stage and to a setting input of a succeeding stage to set the first and second transistors of the succeeding stage to their saturated state when a clock pulse is applied to said third transistor if the first and second transistors of its stage are in their saturated state, and the fourth transistor of each stage being coupled to a resetting input of its stage and to an output of the succeeding stage for resetting the first and second transistors of its stage to their nonconductive cutoff state if the first and second transistors of the succeeding stage are set to their saturated conductive state.

Claim 16

The arrangement as recited in claim 12 wherein each stage includes a clockable fifth transistor coupled to the third transistor of a succeeding stage for inhibiting said third transistor from being switched to its conductive state when said fifth transistor is switched to its conductive state.

Claim 17

The arrangement as recited in claim 13 wherein said n stages are connected to said source of potential whereby a stage stores a first binary value when its first and second transistors and the fourth transistor of a preceding stage are in their saturated conductive states.

Claim 18

The arrangement as recited in claim 14 wherein each stage includes sixth, seventh and eighth transistors coupled between the stage and a preceding stage, whereby in response to a clock pulse applied to said sixth and seventh transistors the first and second transistors of the preceding stage are switched to their conductive state, and said eighth transistors reset the first and second transistors of its stage when the first and second transistors of the preceding stage are switched to their saturated conductive states.