US4498072A
Expired / Lapsed
US
⏱️ 0.0 years remaining
A/D Converter having a self-bias circuit
Assignee: Victor Company of Japan Ltd
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Filing: 1982-06-07
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Granted: 1985-02-05
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Expires: 2002-06-07
Abstract
Abstract A self-bias circuit is employed for automatically changing the reference voltage of a comparator of an A/D converter of successive approximation type. The self-bias circuit is responsive to a voltage at a summing point where an input analog signal, an offset bias and an output analog signal from a D/A converter are added to each other. The self-bias circuit comprises a resistor and a capacitor so that the capacitor is charged by an average current passing through the resistor connected to the summing point, and the voltage across the capacitor will be used as the reference voltage of the comparator. When the input analog signal amplitude is small, the reference voltage is shifted so that noises superposed on the voltage at the summing point does not cause the comparator to produce an erroneous output signal with which the state of the MSB is undesirably changed. As the amplitude increases, the reference voltage rises for ensuring sufficient dynamic range and symmetrical operation for both positive and negative waves.
Inventors
- 👤 Masaru Moriyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 09:12
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/40; H03M1/46
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
184 words
An A/D converter comprising: (a) a comparator for comparing an input analog signal with a reference signal to produce an output signal when said analog signal is greater than said reference signal, said comparator having two input terminals respectively receiving said input analog signal and said reference signal; (b) a successive approximation register responsive to clock pulses and to said output signal from said comparator for producing a digital signal having a predetermined number of bits; (c) a D/A converter responsive to said digital signal to produce an output analog signal; (d) an offset bias circuit for producing a predetermined offset bias voltage; (e) a summing circuit for supplying said comparator with the summation of said input analog signal, said output analog signal from said D/A converter and said offset bias voltage; and (f) a self-bias circuit connected to said two input terminals of said comparator for changing said reference signal in accordance with said summation, said self-bias circuit comprising a resistor interposed between said two input terminals of said comparator, and a capacitor interposed between one of said two input terminals and ground.
Claim 2
Dependent Claim
184 words
An A/D converter comprising: (a) a comparator for comparing an input analog signal with a reference signal to produce an output signal when said analog signal is greater than said reference signal, said comparator having two input terminals respectively receiving said input analog signal and said reference signal; (b) a successive approximation register responsive to clock pulses and to said output signal from said comparator for producing a digital signal having a predetermined number of bits; (c) a D/A converter responsive to said digital signal to produce an output analog signal; (d) an offset bias circuit for producing a predetermined offset bias voltage; (e) a summing circuit for supplying said comparator with the summation of said input analog signal, said output analog signal from said D/A converter and said offset bias voltage; and (f) a self-bias circuit connected to said two input terminals of said comparator for changing said reference signal in accordance with said summation, said self-bias circuit comprising a resistor interposed between said two input terminals of said comparator, and a capacitor interposed between one of said two input terminals and ground.
Claim 3
Dependent Claim
32 words
An A/D converter as claimed in claim 1, wherein said offset bias circuit comprises a voltage source and an inverting circuit for inverting the polarity of the voltage from said voltage source.
Claim 4
Dependent Claim
25 words
An A/D converter as claimed in claim 2, wherein said inverting circuit comprises an operational amplifier associated with an input resistor and a feedback resistor.
Claim 5
Dependent Claim
42 words
An A/D converter as claimed in claim 3, wherein said input resistor and said feedback resistor are so selected that the reference voltage applied to said comparator assumes either positive or negative polarity irrespective of the amplitude of said input analog signal.
Claim 6
Dependent Claim
234 words
An A/D converter comprising: (a) a comparator for comparing an input analog signal with a reference signal to produce an output signal when said analog signal is greater than said reference signal, said comparator having first and second input terminals respectively receiving said input analog signal and said reference signal; (b) a successive approximation register responsive to clock pulses and to said output signal from said comparator for producing a digital signal having a predetermined number of bits; (c) a D/A converter responsive to said digital signal to produce an output analog signal; (d) an offset bias circuit for producing a predetermined offset bias voltage; (e) a summing circuit for supplying said first input terminal of said comparator with the summation of said input analog signal, said output analog signal from said D/A converter and said offset bias voltage, said summing circuit having a first resistor for passing said input analog signal therethrough and a second resistor connected to said offset bias circuit; and (f) a self-bias circuit connected to said two input terminals of said comparator for changing said reference signal in accordance with said summation, said self-bias circuit having a third resistor interposed between said first and second input terminals of said comparator, and a capacitor interposed between said second input terminal and ground, said second input terminal of said comparator being connected via a fourth resistor to said offset bias circuit.
Claim 7
Dependent Claim
234 words
An A/D converter comprising: (a) a comparator for comparing an input analog signal with a reference signal to produce an output signal when said analog signal is greater than said reference signal, said comparator having first and second input terminals respectively receiving said input analog signal and said reference signal; (b) a successive approximation register responsive to clock pulses and to said output signal from said comparator for producing a digital signal having a predetermined number of bits; (c) a D/A converter responsive to said digital signal to produce an output analog signal; (d) an offset bias circuit for producing a predetermined offset bias voltage; (e) a summing circuit for supplying said first input terminal of said comparator with the summation of said input analog signal, said output analog signal from said D/A converter and said offset bias voltage, said summing circuit having a first resistor for passing said input analog signal therethrough and a second resistor connected to said offset bias circuit; and (f) a self-bias circuit connected to said two input terminals of said comparator for changing said reference signal in accordance with said summation, said self-bias circuit having a third resistor interposed between said first and second input terminals of said comparator, and a capacitor interposed between said second input terminal and ground, said second input terminal of said comparator being connected via a fourth resistor to said offset bias circuit.
Claim 8
Dependent Claim
40 words
An A/D converter as claimed in any one of the preceding claims, wherein said self-bias circuit has a time constant which is set to a value much greater than the period of the lowest frequency of said input analog signal.
Claim 9
Dependent Claim
40 words
An A/D converter as claimed in claims 1, 2, 3, 4 or 5, wherein said self-bias circuit has a time constant which is set to a value corresponding to a period of a frequency which is lower than audio frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-02-05 | 1988-08-06 | 1989-02-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-02-05 | 1992-08-06 | 1993-02-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-02-05 | 1996-08-06 | 1997-02-05 | $7700.00 | Window Closed / Lapsed |