Dynamic zero offset compensating circuit for A/D converter

Claim 1

In an analog device having at least one input and one output and receiving an analog signal with a zero mean value, at said input and supplying at its output a signal having a determined relationship with the input signal, an improved compensation circuit for compensating for the zero offset level introduced into the output signal by the device, comprising: means for providing a signal indicative of the sign of the output signal with respect to the real zero, generating means for generating a first control signal during the time-periods when the signs with respect to the offset zero and the real zero are different and when the offset zero crossing in the positive direction precedes the real zero crossing in the positive direction, generating means for generating a second control signal during the time periods when then signs with respect to the offset zero and the real zero are different and when the real zero crossing in the positive direction precedes the offset zero crossing in the positive direction, a storage capacitor having a first terminal M and a second terminal connected to a reference voltage, charging means for charging the capacitor with a current I during the times defined by the first control signal, discharging means for discharging the capacitor with a current -I during the times defined by the second control signal, and means for adding the voltage generated at point M in response to the charge and discharge of said storing capacitor, to the input signal.