Servobalanced delta modulator

Claim 1

In a delta modulator having: a clock (11) for generating sampling signals every T seconds and every T seconds but phase delayed by Tau seconds; a first integrator (R1, C1); an input signal source (25); a current source (S1, S2) connectable to the first integrator; means (23) for generating a relative magnitude difference signal between the input signal source and the first integrator output; means (31, 19, 21, 29) including the current source and a first digitizer (19) responsive to the difference signal and operable by the clock every T seconds for altering the first integrator output by a fixed magnitude I in a direction tending to minimize the difference signal, the polarity of the fixed magnitude corresponding to the binary sign of the first digitizer output; compensation means (31, 17, 13, 27, R2, C2) including a second digitizer (17) also responsive to the difference signal and operable by the clock every T seconds but phase delayed by Tau seconds; said compensation means further comprising: a second integrator (R2, C2) having a time constant Tau 2, Tau 2 > T; the second integrator being coupled to the second digitizer and being incremented in the same direction as the binary signal therefrom; and means (S2) responsive to the second integrator output for varying the first integrator output by an amount Delta I < OR = I square root 2T/ Tau 2, whereby the limits between which the magnitude drift occurs (FIGS. 3a, 3b) varies inversely as the phase delay Tau between the sampling signals.