Expanded analog-to-digital converter having one-half LSB shift

Claim 2

An analog-to-digital converter, comprising a first digital-to-analog converter for converting the most significant bits of a digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is other than zero; a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; and logic means coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero; wherein the second digital-to-analog converter is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

Claim 3

An analog-to-digital converter, comprising an eight-bit digital-to-analog converter for converting the eight most significant bits of a ten-bit digital output signal to a first analog reference signal having a value that is proportional to the value of the eight most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is other than zero; a two-bit digital-to-analog converter for converting the two least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the eight most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the two least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; and logic means coupled to the successive approximation register for providing an indication of whether the value of the eight most significant bits is other than zero; wherein the two-bit digital-to-analog converter is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the two least significant bits whenever the value of the eight most significant bits is other than zero, and a value that is proportional to the value of the two least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is zero.

Claim 4

An analog-to-digital converter, comprising an eight-bit digital-to-analog converter for converting the eight most significant bits of a ten-bit digital output signal to a first analog reference signal having a value that is proportional to the value of the eight most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is other than zero; a two-bit digital-to-analog converter for converting the two least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the eight most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the two least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; and logic means coupled to the successive approximation register for providing an indication of whether the value of the eight most significant bits is other than zero; wherein the two-bit digital-to-analog converter is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the two least significant bits whenever the value of the eight most significant bits is other than zero, and a value that is proportional to the value of the two least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is zero.

Claim 5

An analog-to-digital converter comprising a first digital-to-analog converter for converting the most significant bits of a digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bit is other than zero; a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; and a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; wherein the second digital-to-analog converter comprises a series resistance network having one end of the network coupled to the output of the first digital-to-analog converter; a current source connected to the other end of the series resistance network; and a decoder circuit including a matrix of switches connected to the nodes of the resistances of the series resistance network, wherein the switches are controllable by the least significant bits of the digital output signal for connecting certain ones of the nodes of the resistances of the series resistance network to provide the second analog reference signal and to add the second analog reference signal to the first analog reference signal for provision to the comparator, and further comprising logic means coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero; wherein the decoder circuit is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

Claim 6

An analog-to-digital converter comprising a first digital-to-analog converter for converting the most significant bits of a digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bit is other than zero; a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; and a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; wherein the second digital-to-analog converter comprises a series resistance network having one end of the network coupled to the output of the first digital-to-analog converter; a current source connected to the other end of the series resistance network; and a decoder circuit including a matrix of switches connected to the nodes of the resistances of the series resistance network, wherein the switches are controllable by the least significant bits of the digital output signal for connecting certain ones of the nodes of the resistances of the series resistance network to provide the second analog reference signal and to add the second analog reference signal to the first analog reference signal for provision to the comparator, and further comprising logic means coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero; wherein the decoder circuit is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

Claim 7

An analog-to-digital converter comprising an eight-bit digital-to-analog converter for converting the eight most significant bits of a ten-bit digital output signal to a first analog reference signal; having a value that is proportional to the value of the eight most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is other than zero; a two-bit digital-to-analog converter for converting the two least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the eight most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the two least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; wherein the two-bit digital-to-analog converter comprises a series resistance network having one end of the network coupled to the output of the first digital-to-analog converter; a current source connected to the other end of the series resistance network; and a decoder circuit including a matrix of switches connected to the nodes of the resistances of the series resistance network, wherein the switches are controllable by the two least significant bits of the digital output signal for connecting certain ones of the nodes of the resistances of the series resistance network to provide the second analog reference signal and to add the second analog reference signal to the first analog reference signal for provision to the comparator; and further comprising logic means coupled to the successive approximation register for providing an indication of whether the value of the eight most significant bits is other than zero; wherein the decoder circuit is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the two least significant bits whenever the value of the eight most significant bits is other than zero; and a value that is proportional to the value of the two least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is zero.

Claim 8

An analog-to-digital converter comprising an eight-bit digital-to-analog converter for converting the eight most significant bits of a ten-bit digital output signal to a first analog reference signal; having a value that is proportional to the value of the eight most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is other than zero; a two-bit digital-to-analog converter for converting the two least significant bits of the digital output signal to a second analog reference signal; a comparator for comparing an analog input signal with the sum of the analog reference signals; a successive approximation register connected to be driven by the comparator for successively providing the bits of the digital output signal beginning with the most significant bit in accordance with said comparison of the analog input signal with the sum of the analog reference signals, for providing the eight most significant bits of the digital output signal to the first digital-to-analog converter to drive the first digital-to-analog converter, and for providing the two least significant bits of the digital output signal to the second digital-to-analog converter to drive the second digital-to-analog converter; wherein the two-bit digital-to-analog converter comprises a series resistance network having one end of the network coupled to the output of the first digital-to-analog converter; a current source connected to the other end of the series resistance network; and a decoder circuit including a matrix of switches connected to the nodes of the resistances of the series resistance network, wherein the switches are controllable by the two least significant bits of the digital output signal for connecting certain ones of the nodes of the resistances of the series resistance network to provide the second analog reference signal and to add the second analog reference signal to the first analog reference signal for provision to the comparator; and further comprising logic means coupled to the successive approximation register for providing an indication of whether the value of the eight most significant bits is other than zero; wherein the decoder circuit is responsive to the indication by the logic means for causing the second analog reference signal to have a value that is proportional to the value of the two least significant bits whenever the value of the eight most significant bits is other than zero; and a value that is proportional to the value of the two least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the eight most significant bits is zero.