Digital error correcting trimming in an analog to digital converter

Claim 2

A digitally trimmed analog-to-digital converter that provides a plural bit digital output word representative of an analog input voltage, said converter comprising: an analog-to-digital converter capable of supplying a plurality of digital output words, each one of which represents a different analog input voltage, said converter including a plurality of dual digital-to-analog converter elements commonly coupled to a comparator having a plurality of capacitor weighted charge balanced input pairs; means for varying the values of said analog voltages representative of particular ones of said digital output words in response to digital trim words by applying correcting voltages to selected inputs of said comparator said digital trim words including an individual trim word for each one of said particular ones of said digital output words; read only memory means for storing said digital trim words; means for addressing said read only memory means with said particular ones of said digital output words; means for applying the digital trim words in said read only memory to said means for varying; means for temporarily bypassing said read only memory; means for applying an externally generated digital trim word to said converter wherein said externally generated word can be manipulated to select a desired trim word; and means for entering said desired trim word into said read only memory.

Claim 3

The converter of claim 1 wherein said means for varying the values of said analog voltages further includes means for varying the weighting of the effect of said digital trim words as a function of the number of bits in said digital output word.

Claim 4

The converter of claim 1 wherein said means for temporarily bypassing comprise: means for disabling said memory means; means for generating a digital trim word and for varying said digital trim word to simulate the contents of said memory; and means for coupling said means for generating to the output portion of said memory means.

Claim 5

The converter of claim 3 further including means for switching said converter from twelve bit to ten bit operation by switching the value of said weighting capacitor in said comparator.

Claim 6

In a method for trimming an integrated circuit analog-to-digital converter in wafer form for producing a digital output word having a plurality of bits and the capability of generating a particular digital word as a function of an applied analog voltage, said converter including a capacitor weighted charge balanced comparator, memory means for storing a plurality of digital trim words, means for addressing said memory as a function of a plurality of the most significant bits of said digital output word, means for varying the response of said converter as a function of said digital trim word, and means for programming said memory means, the process steps comprising: locating said wafer in a probe equipped step and repeat machine; rendering said converter operative; applying an analog voltage to obtain a digital output word that includes all of said most significant bits; calculating the analog voltage that should be present in response to said digital word; temporarily bypassing said memory means; generating a digital trim word to simulate the contents of said memory; varying said generated trim word until said analog voltage most nearly equals said calculated value for said word; repeating said steps of applying, calculating, generating and varying for each separate digital output word that represents a combination of said most significant bits; and entering said words obtained in the preceding steps to program said memory means whereby said converter is trimmed.

Claim 7

In a method for trimming an integrated circuit analog-to-digital converter in wafer form for producing a digital output word having a plurality of bits and the capability of generating a particular digital word as a function of an applied analog voltage, said converter including a capacitor weighted charge balanced comparator, memory means for storing a plurality of digital trim words, means for addressing said memory as a function of a plurality of the most significant bits of said digital output word, means for varying the response of said converter as a function of said digital trim word, and means for programming said memory means, the process steps comprising: locating said wafer in a probe equipped step and repeat machine; rendering said converter operative; applying an analog voltage to obtain a digital output word that includes all of said most significant bits; calculating the analog voltage that should be present in response to said digital word; temporarily bypassing said memory means; generating a digital trim word to simulate the contents of said memory; varying said generated trim word until said analog voltage most nearly equals said calculated value for said word; repeating said steps of applying, calculating, generating and varying for each separate digital output word that represents a combination of said most significant bits; and entering said words obtained in the preceding steps to program said memory means whereby said converter is trimmed.

Claim 8

The process of claim 5 wherein said converter is a twelve bit device and said memory is addressed by the four most significant bits.

Claim 9

The method of claim 6 including the step of switching said converter to ten bit operation.