US4227185A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single chip integrated analog-to-digital converter circuit powered by a single voltage potential
Assignee: Texas Instruments Inc
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Filing: 1978-11-29
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Granted: 1980-10-07
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Expires: 1998-11-29
Abstract
Abstract A novel analog-to-digital converter is integrated on a semiconductor substrate utilizing I 2 L techniques. The resulting converter, which utilizes dual slope integration to generate a digital signal, operates from a single low-voltage power supply and has few external components. The converter is suitable for integration with I 2 L digital circuitry to provide a complete digital system, which operates in accordance with an analog input signal, on a single semiconductor chip.
Inventors
- 👤 John W. Kronlage
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:25
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1009; H03M1/1028; G; G01; G01K; G01K1/00; G01K1/02; G01K1/028; H03M1/1033; H03M1/1057; H03M1/1061; H03M1/12; H03M1/50; H03M1/52
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
332 words
A single chip integrated dual slope analog-to-digital converter circuit comprising: (a) first terminal means for receiving a relatively low voltage potential, wherein said integrated circuit operates entirely from a single voltage potential applied to said first terminal means; (b) second terminal means for receiving analog input signals; (c) scaling amplifier means coupled to said first and second terminal means for generating a first voltage which is a representation of received analog input signals; (d) reference amplifier means coupled to said first terminal means for generating a second voltage representative of the full scale of the received analog input signals; (e) integrator means having input and output means and means for coupling an integration capacitor thereto, said integrator means for generating a ramp voltage in one direction when said first voltage is applied to the input means thereof and for generating a ramp voltage in the opposite direction when said second voltage is applied to the input means thereof; (f) controllable switch means for selectively applying either said first or second voltage to the input means of said integrator; (g) comparator means coupled to the output means of said integrator means and to said first terminal means for producing a logical transition signal when said integrator ramp voltage crosses a threshold voltage in either direction; (h) triggerable storage means coupled to said comparator means, and responsive to said transition signal for storing an indication of the occurrence thereof; (i) digital counter means for generating a digital count; (j) means coupled to said counter means, and responsive to the indication stored in said triggerable storage means for storing said digital count upon the occurrence of said transition signal, said storage digital count being a digital representation of the analog input signals applied to said second terminal means; (k) voltage regulator means coupling said first terminal means to said scaling amplifier means, said reference amplifier means, said integrator means and said comparator means for regulating the low-voltage reference potential applied to each of said means.
Claim 2
Dependent Claim
332 words
A single chip integrated dual slope analog-to-digital converter circuit comprising: (a) first terminal means for receiving a relatively low voltage potential, wherein said integrated circuit operates entirely from a single voltage potential applied to said first terminal means; (b) second terminal means for receiving analog input signals; (c) scaling amplifier means coupled to said first and second terminal means for generating a first voltage which is a representation of received analog input signals; (d) reference amplifier means coupled to said first terminal means for generating a second voltage representative of the full scale of the received analog input signals; (e) integrator means having input and output means and means for coupling an integration capacitor thereto, said integrator means for generating a ramp voltage in one direction when said first voltage is applied to the input means thereof and for generating a ramp voltage in the opposite direction when said second voltage is applied to the input means thereof; (f) controllable switch means for selectively applying either said first or second voltage to the input means of said integrator; (g) comparator means coupled to the output means of said integrator means and to said first terminal means for producing a logical transition signal when said integrator ramp voltage crosses a threshold voltage in either direction; (h) triggerable storage means coupled to said comparator means, and responsive to said transition signal for storing an indication of the occurrence thereof; (i) digital counter means for generating a digital count; (j) means coupled to said counter means, and responsive to the indication stored in said triggerable storage means for storing said digital count upon the occurrence of said transition signal, said storage digital count being a digital representation of the analog input signals applied to said second terminal means; (k) voltage regulator means coupling said first terminal means to said scaling amplifier means, said reference amplifier means, said integrator means and said comparator means for regulating the low-voltage reference potential applied to each of said means.
Claim 3
Dependent Claim
18 words
The analog-to-digital converter circuit according to claim 1, wherein the integrator circuit is comprised of bipolar transistor circuitry.
Claim 4
Dependent Claim
31 words
The analog-to-digital converter circuit according to claim 1, wherein said counter means and said means for storing the count of said counter means are comprised of current injection logic digital circuitry.
Claim 5
Dependent Claim
37 words
The analog-to-digital converter circuit according to claim 3, wherein said counter means and said means for storing the count of said counter means are coupled to said first terminal means, and are powered by said low-voltage potential.
Claim 6
Dependent Claim
24 words
The analog-to-digital converter circuit integrated circuit according to claim 1, wherein said circuitry is integrated in an N-type epitaxial layer on a P-type substrate.
Claim 7
Dependent Claim
21 words
The analog-to-digital converter integrated circuit according to claim 5, wherein said epitaxial layer is between 0.2 and 0.3 mils in thickness.
Claim 8
Dependent Claim
22 words
The analog-to-digital converter circuit according to claim 6 including decoder means coupled to said counter means for controlling said controllable switch means.
Claim 9
Dependent Claim
39 words
The analog-to-digital converter circuit according to claim 1 including second controllable switch means coupled to said means for receiving an integration capacitor to said integrator, and said triggerable storage means for discharging said integration capacitor to initialize said converter.
Claim 10
Dependent Claim
23 words
The analog-to-digital converter circuit according to claim 8 including decoder means coupled to said counter means for controlling said second controllable switch means.
Claim 11
Dependent Claim
22 words
The analog-to-digital converter circuit according to claim 1, wherein said single voltage potential is on the order of 5 volts or less.
Claim 12
Dependent Claim
318 words
A single chip integrated dual slope analog-to-digital converter circuit comprising: (a) first terminal means for receiving a relatively low voltage potential, wherein said integrated circuit operates entirely from a single voltage potential applied to said first terminal means; (b) regulator means coupled to said first terminal means for producing a reference voltage which does not substantially vary with changes in ambient conditions; (c) second terminal means for receiving analog input signals; (d) scaling amplifier means coupled to said regulator means and to said second means for generating a first voltage which is a representation of received analog input signals; (e) reference amplifier means coupled to said regulator means for generating a second voltage representative of the full scale of the received analog input signals; (f) integrator means coupled to said regulator means and having input and output means, said integrator means for generating a ramp voltage in one direction when said first voltage is applied to the input means thereof and for generating a ramp voltage in the opposite direction when said second voltage is applied to the input means thereof; (g) controllable switch means for selectively applying either said first or second voltage to the input means of said integrator; (h) comparator means coupled to the output means of said integrator means and to said regulator means for producing a logical transition signal when said integrator ramp voltage crosses a threshold voltage in either direction; (i) triggerable storage means coupled to said comparator means, and responsive to said transition signal for storing an indication of the occurrence thereof; (j) digital counter means for generating a digital count; and (k) means coupled to said counter means, and responsive to the indication stored in said triggerable storage means for storing said digital count upon the occurrence of said transition signal, said stored digital count being a digital representation of the analog input signals applied to said second terminal means.
Claim 13
Dependent Claim
318 words
A single chip integrated dual slope analog-to-digital converter circuit comprising: (a) first terminal means for receiving a relatively low voltage potential, wherein said integrated circuit operates entirely from a single voltage potential applied to said first terminal means; (b) regulator means coupled to said first terminal means for producing a reference voltage which does not substantially vary with changes in ambient conditions; (c) second terminal means for receiving analog input signals; (d) scaling amplifier means coupled to said regulator means and to said second means for generating a first voltage which is a representation of received analog input signals; (e) reference amplifier means coupled to said regulator means for generating a second voltage representative of the full scale of the received analog input signals; (f) integrator means coupled to said regulator means and having input and output means, said integrator means for generating a ramp voltage in one direction when said first voltage is applied to the input means thereof and for generating a ramp voltage in the opposite direction when said second voltage is applied to the input means thereof; (g) controllable switch means for selectively applying either said first or second voltage to the input means of said integrator; (h) comparator means coupled to the output means of said integrator means and to said regulator means for producing a logical transition signal when said integrator ramp voltage crosses a threshold voltage in either direction; (i) triggerable storage means coupled to said comparator means, and responsive to said transition signal for storing an indication of the occurrence thereof; (j) digital counter means for generating a digital count; and (k) means coupled to said counter means, and responsive to the indication stored in said triggerable storage means for storing said digital count upon the occurrence of said transition signal, said stored digital count being a digital representation of the analog input signals applied to said second terminal means.
Claim 14
Dependent Claim
18 words
The analog-to-digital converter circuit according to claim 11, wherein the integrator circuit is comprised of bipolar transistor circuitry.
Claim 15
Dependent Claim
31 words
The analog-to-digital converter circuit according to claim 11, wherein said counter means and said means for storing the count of said counter means are comprised of current injection logic digital circuitry.
Claim 16
Dependent Claim
37 words
The analog-to-digital converter circuit according to claim 13, wherein said counter means and said means for storing the count of said counter means are coupled to said first terminal means, and are powered by said low-voltage potential.
Claim 17
Dependent Claim
24 words
The analog-to-digital converter circuit integrated circuit according to claim 11, wherein said circuitry is integrated in an N-type epitaxial layer on a P-type substrate.
Claim 18
Dependent Claim
20 words
The analog-to-digital converter circuit according to claim 15, wherein said epitaxial layer is between 0.2 and 0.3 mils in thickness.
Claim 19
Dependent Claim
22 words
The analog-to-digital converter circuit according to claim 16 including decoder means coupled to said counter means for controlling said controllable switch means.
Claim 20
Dependent Claim
38 words
The analog-to-digital converter circuit according to claim 11 including second controllable switch means coupled to said integrator means, and said triggerable storage means for discharging an integration capacitor coupled to said integrated analog-to-digital converter to initialize said converter.
Claim 21
Dependent Claim
22 words
The analog-to-digital converter according to claim 18 including decoder means coupled to said counter means for controlling said second controllable switch means.
Claim 22
Dependent Claim
22 words
The analog-to-digital converter circuit according to claim 11, wherein said single voltage potential is on the order of 5 volts or less.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-10-07 | 1984-04-07 | 1984-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-10-07 | 1988-04-07 | 1988-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-10-07 | 1992-04-07 | 1992-10-07 | $7700.00 | Window Closed / Lapsed |